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ps024315-1011 copyright ?2011 zilog ? , inc. all rights reserved. www.zilog.com product specification high-performance 8-b it microcontrollers z8 encore! xp ? f0823 series
ps024315-1011 p r e l i m i n a r y disclaimer z8 encore! xp ? f0823 series product specification ii do not use this product in life support systems. life support policy zilog?s products are not authorized for use as critical components in life support devices or systems without th e express prior written approval of the president and general counsel of zilog corporation. as used herein life support devices or systems are devices which (a) are intended for surgical impl ant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a signi ficant injury to the user. a criti- cal component is any component in a life support device or system whose failure to perform can be reason- ably expected to cause the failure of the life support devi ce or system or to affect its safety or effectiveness. document disclaimer ?2011 zilog, inc. all rights reserved . information in this publication co ncerning the devices, applications, or technology described is intend ed to suggest possible uses and may be superseded. zilog, inc. does not assume liability for or provide a representation of accuracy of the information, devices, or technology described in this document. zilog also does not assume liability for intellectual property infringement related in any manner to use of information, devices, or technology described herein or otherwise. the information contained w ithin this document has been verified according to the general principles of electrical and mechanical engineering. z8, z8 encore! and z8 encore! xp are trademarks or registered trademarks of zilog, inc. all other product or service names are the property of their respective owners. warning:
ps024315-1011 p r e l i m i n a r y revision history z8 encore! xp ? f0823 series product specification iii revision history each instance in this document?s revision history reflects a change from its previous edi- tion. for more details, refer to the corresponding page(s) or appropriate links furnished in the table below. date revision level chapter/section description page no. sep 15 led drive enable register clarifie d statement surrounding the alternate function register as it relates to the led function; revised flash sector protect regis- ter description; revised packaging chapter. 51 , 144 , 210 mar 2008 14 n/a changed branding to z8 encore! xp f0823 series where appropriate. all dec 2007 13 pin description, general-pur- pose input/output, interrupt controller, watchdog timer, electrical characteristics, and ordering information updated title from z8 encore! 8k and 4k series to z8 encore! xp Z8F0823 series . updated figure 3, table 15, table 35, tables 59 through 61, table 119 and part number suffix designations section. 8 , 36 , 60 , 95 , 199 , and 220 aug 2007 12 part selection guide, external clock setup, and program memory updated table 1, table 16, and program memory section. 2 , 35 , and 13 jun 2007 11 n/a updated to combine z8 encore! 8k and z8 encore! 4k series. all dec 2006 10 ordering information updated ordering information chapter. 211
ps024315-1011 p r e l i m i n a r y table of contents z8 encore! xp ? f0823 series product specification iv table of contents revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iii list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 part selection guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 cpu and peripheral overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 general-purpose i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 flash controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 internal precision oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 10-bit analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 analog comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 universal asynchronous receiver/transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 reset controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 on-chip debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 available packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 register file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 flash information area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 reset and stop mode recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 reset types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 voltage brown-out reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 watchdog timer reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
ps024315-1011 p r e l i m i n a r y table of contents z8 encore! xp ? f0823 series product specification v external reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 external reset indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 on-chip debugger initiated reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 stop mode recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 stop mode recovery using watchdog timer time-o ut . . . . . . . . . . . . . . . . . . . . . 27 stop mode recovery using a gpio port pin transition . . . . . . . . . . . . . . . . . . . . . 27 stop mode recovery usin g the external reset pin . . . . . . . . . . . . . . . . . . . . . . . 28 reset register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 peripheral-level power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 power control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 general-purpose input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 gpio port availability by device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 gpio alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 direct led drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 shared reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 shared debug pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 9 crystal oscillator override . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5 v tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 external clock setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 gpio interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 gpio control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 port a?c address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 port a?c control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 port a?c data direction subregisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 port a?c alternate function subregis ters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 port a?c input data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 port a?c output data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 led drive enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 led drive level high register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 led drive level low register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 interrupt vector listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 master interrupt enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 interrupt vectors and priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
ps024315-1011 p r e l i m i n a r y table of contents z8 encore! xp ? f0823 series product specification vi interrupt assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 software interrupt assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 watchdog timer interrupt as sertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 interrupt control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 interrupt request 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 interrupt request 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 interrupt request 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 irq0 enable high and low bit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 irq1 enable high and low bit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 irq2 enable high and low bit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 interrupt edge select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 shared interrupt select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 interrupt control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 timer operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 reading the timer count values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 timer pin signal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 timer control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 timer 0?1 high and low byte registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 timer reload high and low byte registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 timer 0?1 pwm high and low byte registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 timer 0?1 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 watchdog timer refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 watchdog timer time-out response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 watchdog timer reload unlo ck sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 watchdog timer control register defi nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 watchdog timer control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 watchdog timer reload upper, high and low by te registers . . . . . . . . . . . . . . . 94 universal asynchronous receiver/transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 transmitting data using the polled method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 transmitting data using the interrupt-driven method . . . . . . . . . . . . . . . . . . . . . 100 receiving data using the polled method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 receiving data using the interrupt -driven method . . . . . . . . . . . . . . . . . . . . . . . 102 clear to send (cts) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
ps024315-1011 p r e l i m i n a r y table of contents z8 encore! xp ? f0823 series product specification vii multiprocessor (9-bit) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 external driver enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 uart interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 uart baud rate generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 uart control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 uart transmit data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 uart receive data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 uart status 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 uart status 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 uart control 0 and control 1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 uart address compare register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 uart baud rate high and low byte registers . . . . . . . . . . . . . . . . . . . . . . . . . . 115 infrared encoder/decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 17 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 transmitting irda data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 receiving irda data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 infrared encoder/decoder control register definitions . . . . . . . . . . . . . . . . . . . . . . . . 120 analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 automatic powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 single-shot conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 continuous conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 calibration and compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 adc control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 adc control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 adc control/status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 adc data high byte register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 adc data low bits register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 comparator control register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 flash information area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 flash operation timing using the flash frequenc y registers . . . . . . . . . . . . . . . 137 flash code protection against external access . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
ps024315-1011 p r e l i m i n a r y table of contents z8 encore! xp ? f0823 series product specification viii flash code protection against accidental prog ram and erasure . . . . . . . . . . . . . 137 byte programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 page erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 mass erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 flash controller bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 flash controller behavior in debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 flash control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 flash status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 flash page select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 flash sector protect register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 flash frequency high and low byte registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 flash option bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 option bit configuration by reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 option bit types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 reading the flash information page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 flash option bit control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 trim bit address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 trim bit data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 flash option bit address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 trim bit address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 zilog calibration data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 adc calibration data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 serialization data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 randomized lot identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 on-chip debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 ocd interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 ocd data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 ocd autobaud detector/generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 ocd serial errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 ocd unlock sequence (8-pin devices only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 runtime counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 on-chip debugger commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 on-chip debugger control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 ocd control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
ps024315-1011 p r e l i m i n a r y table of contents z8 encore! xp ? f0823 series product specification ix ocd status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 oscillator control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 system clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 clock failure detection and recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 oscillator control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 internal precision oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 ez8 cpu instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 assembly language programming introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 assembly language syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 ez8 cpu instruction notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 ez8 cpu instruction classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 ez8 cpu instruction summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 opcode maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 0 on-chip peripheral ac and dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 201 general purpose i/o port input da ta sample timing . . . . . . . . . . . . . . . . . . . . . . 204 general purpose i/o port output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 on-chip debugger timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 uart timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 part number suffix designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 customer support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
ps024315-1011 p r e l i m i n a r y list of figures z8 encore! xp ? f0823 series product specification x list of figures figure 1. z8 encore! xp f0823 series block diagram . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 2. z8f08x3, z8f04x3, f02x3 an d z8f01x3 in 8-pin soic, qfn/mlf-s, ? or pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. z8f08x3, z8f04x3, f02x 3 and z8f01x3 in 20-pin soic, ssop ? or pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. z8f08x3, z8f04x3, f02x 3 and z8f01x3 in 28-pin soic, ssop ? or pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 5. power-on reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 6. voltage brown-out reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 7. gpio port pin block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 8. interrupt controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 9. timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 10. uart block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 11. uart asynchronous data format without parity . . . . . . . . . . . . . . . . . . . 99 figure 12. uart asynchronous data format with pa rity . . . . . . . . . . . . . . . . . . . . . . 99 figure 13. uart asynchronous multiprocess or mode data format . . . . . . 103 figure 14. uart driver enable signal timing (shown with 1 stop bit and parity) 105 figure 15. uart receiver interrupt service routine flow . . . . . . . . . . . . . . . . . . . 107 figure 16. infrared data communi cation system block diagram . . . . . . . . . . . . . . 117 figure 17. infrared data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 figure 18. irda data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 figure 19. analog-to-digital conver ter block diagram . . . . . . . . . . . . . . . . . . . . . . 122 figure 20. flash memory arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 figure 21. flash controller operation flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 figure 22. on-chip debugger block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 figure 23. interfacing the on-chip debugg er?s dbg pin with an rs-232 interface, ? # 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 figure 24. interfacing the on-chip debugg er?s dbg pin with an rs-232 interface, ? # 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 figure 25. ocd data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 figure 26. opcode map cell description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 figure 27. first opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 figure 28. second opcode map after 1fh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 figure 29. port input sample timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
ps024315-1011 p r e l i m i n a r y list of figures z8 encore! xp ? f0823 series product specification xi figure 30. gpio port output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 figure 31. on-chip debugger timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 figure 32. uart timing with cts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 figure 33. uart timing without cts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
ps024315-1011 p r e l i m i n a r y list of tables z8 encore! xp ? f0823 series product specification xii list of tables table 1. f0823 series family part selection guide . . . . . . . . . . . . . . . . . . . . . . . . . . 2 table 2. f0823 series package options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 4. pin characteristics (20- and 28-pin devices )* . . . . . . . . . . . . . . . . . . . . . . 11 table 5. pin characteristics (8-pin devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 6. z8 encore! xp f0823 series program me mory maps . . . . . . . . . . . . . . . . 14 table 7. f0823 series flash memory information area map . . . . . . . . . . . . . . . . . . 15 table 8. register file address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 9. reset and stop mode recovery character istics and latency . . . . . . . . . . . 21 table 10. reset sources and resulting reset type . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 11. stop mode recovery so urces and resulting action . . . . . . . . . . . . . . . . . . 27 table 12. reset status register (rststat) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 13. por indicator values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 14. power control register 0 (pwrctl0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 15. port availability by device and package type . . . . . . . . . . . . . . . . . . . . . . 33 table 16. port alternate function mapping (8-pin parts) . . . . . . . . . . . . . . . . . . . . . . 35 table 17. port alternate function mapping (non 8-pi n parts) . . . . . . . . . . . . . . . . . . 36 table 18. gpio port registers and subregisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 19. port a?c gpio address registers (pxaddr) . . . . . . . . . . . . . . . . . . . . . . 41 table 20. paddr[7:0] subregister functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 21. port a?c control registers (pxctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 22. port a?c data direction subregisters (px dd) . . . . . . . . . . . . . . . . . . . . . . 43 table 23. port a?c alternate functio n subregisters (pxaf) . . . . . . . . . . . . . . . . . . . 44 table 24. port a?c output control subregisters (pxoc) . . . . . . . . . . . . . . . . . . . . . . 44 table 25. port a?c high drive enable subregisters (phdex) . . . . . . . . . . . . . . . . . 45 table 26. port a?c stop mode recovery source enable subregisters (psmrex) . . 46 table 27. port a?c pull-up enable subregisters (ppuex) . . . . . . . . . . . . . . . . . . . . 47 table 28. port a?c alternate func tion set 1 subregisters (pafs1x) . . . . . . . . . . . . 48 table 29. port a?c alternate func tion set 2 subregisters (pxafs2) . . . . . . . . . . . . 49 table 30. port a?c input data registers (pxin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 31. port a?c output data register (pxout) . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 32. led drive enable (leden) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 33. led drive level high register (ledlvlh ) . . . . . . . . . . . . . . . . . . . . . . 52
ps024315-1011 p r e l i m i n a r y list of tables z8 encore! xp ? f0823 series product specification xiii table 34. led drive level low register (ledlvll) . . . . . . . . . . . . . . . . . . . . . . . 53 table 35. trap and interrupt vectors in order of prio rity . . . . . . . . . . . . . . . . . . . . . . 55 table 36. interrupt request 0 register (irq0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 37. interrupt request 1 register (irq1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 38. interrupt request 2 register (irq2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 39. irq0 enable and priority encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 40. irq0 enable high bit register (irq0enh) . . . . . . . . . . . . . . . . . . . . . . . 62 table 41. irq0 enable low bit register (irq0enl) . . . . . . . . . . . . . . . . . . . . . . . . 62 table 42. irq1 enable and priority encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 43. irq1 enable low bit register (irq1enl) . . . . . . . . . . . . . . . . . . . . . . . . 64 table 44. irq1 enable high bit register (irq1enh) . . . . . . . . . . . . . . . . . . . . . . . 64 table 45. irq2 enable and priority encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 46. irq2 enable high bit register (irq2enh) . . . . . . . . . . . . . . . . . . . . . . . 65 table 47. irq2 enable low bit register (irq2enl) . . . . . . . . . . . . . . . . . . . . . . . . 66 table 48. interrupt edge select register (irqes) . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 49. shared interrupt select register (irqss) . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 50. interrupt control register (irqctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 51. timer 0?1 high byte register (txh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 52. timer 0?1 low byte register (txl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 53. timer 0?1 reload high byte register (t xrh) . . . . . . . . . . . . . . . . . . . . . . 85 table 54. timer 0?1 reload low byte register (txr l) . . . . . . . . . . . . . . . . . . . . . . 85 table 55. timer 0?1 pwm high byte register (txpwmh) . . . . . . . . . . . . . . . . . . . 86 table 56. timer 0?1 pwm low byte register (txpwml) . . . . . . . . . . . . . . . . . . . . 86 table 57. timer 0?1 control register 0 (txctl0) . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 58. timer 0?1 control register 1 (txctl1) . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 59. watchdog timer approximate time-out de lays . . . . . . . . . . . . . . . . . . . . 91 table 60. watchdog timer control register (wdtctl) . . . . . . . . . . . . . . . . . . . . . 94 table 61. watchdog timer reload upper byte register (wdtu) . . . . . . . . . . . . . . 95 table 62. watchdog timer reload high byte regi ster (wdth) . . . . . . . . . . . . . . . 95 table 63. watchdog timer reload low byte regist er (wdtl) . . . . . . . . . . . . . . . . 95 table 64. uart transmit data register (u0txd) . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 65. uart receive data register (u0rxd) . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 66. uart status 0 register (u0stat0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 67. uart status 1 register (u0stat1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 68. uart control 0 register (u0ctl0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 69. uart control 1 register (u0ctl1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
ps024315-1011 p r e l i m i n a r y list of tables z8 encore! xp ? f0823 series product specification xiv table 70. uart address compare register (u0addr) . . . . . . . . . . . . . . . . . . . . . 115 table 71. uart baud rate high byte register (u0brh) . . . . . . . . . . . . . . . . . . . 115 table 72. uart baud rate low byte register (u0brl) . . . . . . . . . . . . . . . . . . . . 115 table 73. uart baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 table 74. adc control register 0 (adcctl0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 table 75. adc control/status register 1 (adcctl1) . . . . . . . . . . . . . . . . . . . . . . 129 table 76. adc data high byte register (adcd_h) . . . . . . . . . . . . . . . . . . . . . . . . 130 table 77. adc data low bits register (adcd_l) . . . . . . . . . . . . . . . . . . . . . . . . . 131 table 78. comparator control register (cmp0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 table 79. z8 encore! xp f0823 series flash me mory configurations . . . . . . . . . . 134 table 80. flash code protection using the flash op tion bits . . . . . . . . . . . . . . . . . 138 table 81. flash control register (fctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 table 82. flash status register (fstat) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 table 83. flash page select register (fps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 table 84. flash sector protect register (fprot) . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 table 85. flash frequency high byte register ( ffreqh) . . . . . . . . . . . . . . . . . . . 145 table 86. flash frequency low byte register (ffr eql) . . . . . . . . . . . . . . . . . . . . 145 table 87. trim bit address register (trmadr) . . . . . . . . . . . . . . . . . . . . . . . . . . 148 table 88. trim bit data register (trmdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 table 89. flash option bits at program memory address 0000h . . . . . . . . . . . . . . 149 table 90. flash options bits at program memory address 0001h . . . . . . . . . . . . . 150 table 91. trim options bits at address 0000h . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 table 92. trim option bits at 0001h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 table 93. trim option bits at 0002h (tipo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 table 94. adc calibration bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 table 95. adc calibration data location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 table 96. serial number at 001c?001f (s_num) . . . . . . . . . . . . . . . . . . . . . . . . . . 154 table 97. serialization data locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 table 98. lot identification number (rand_lot) . . . . . . . . . . . . . . . . . . . . . . . . 154 table 99. randomized lot id locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 table 100. ocd baud-rate limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 table 101. ocd commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 table 102. ocd control register (ocdctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 table 103. ocd status register (ocdstat) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 table 104. oscillator configuration and selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 table 105. oscillator control register (oscctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
ps024315-1011 p r e l i m i n a r y list of tables z8 encore! xp ? f0823 series product specification xv table 106. assembly language syntax example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 175 table 107. assembly language syntax example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 176 table 108. notational shorthand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 table 109. additional symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 table 110. arithmetic instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 table 111. bit manipulation instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 table 112. block transfer instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 table 113. cpu control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 table 114. load instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 table 115. logical instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 table 116. program control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 table 117. rotate and shift instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 table 118. ez8 cpu instruction summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 table 119. opcode map abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 table 120. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 table 121. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 table 122. power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 table 123. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 table 124. internal precision oscillator electrical characteristics . . . . . . . . . . . . . . . 200 table 125. power-on reset and voltage br own-out electrical characteristics ? and timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 table 126. flash memory electrical characteristic s and timing . . . . . . . . . . . . . . . . 202 table 127. watchdog timer electrical characteri stics and timing . . . . . . . . . . . . . . 202 table 128. analog-to-digital converter electrical characteristics and timing . . . . . 203 table 129. comparator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 table 130. gpio port input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 table 131. gpio port output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 table 132. on-chip debugger timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 table 133. uart timing with cts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 table 134. uart timing without cts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 table 135. z8 encore! xp f0823 series ordering ma trix . . . . . . . . . . . . . . . . . . . . . 211
ps024315-1011 p r e l i m i n a r y overview z8 encore! xp ? f0823 series product specification 1 overview zilog?s z8 encore! xp microc ontroller unit (mcu) family of products are the first zilog microcontroller products based on the 8-bit ez8 cpu core. z8 encore! xp f0823 series products expand upon zilog?s extensive line of 8-bit microcon trollers. the flash in-circuit programming capability allows for faster de velopment time and prog ram changes in the field. the new ez8 cpu is upward compatible with existing z8 instructions. the rich peripheral set of z8 encore! xp f0823 seri es makes it suitable for a variety of applica- tions including motor co ntrol, security systems, home ap pliances, personal electronic devices, and sensors. features the key features of z8 encore! xp f0823 series include: ? 5 mhz ez8 cpu ? 1 kb, 2 kb, 4 kb, or 8 kb flash memory with in-circuit programming capability ? 256 b, 512 b, or 1 kb register ram ? 6 to 24 i/o pins depending upon package ? internal precision oscillator (ipo) ? full-duplex uart ? the universal asynchronous re ceiver/transmitter (uart) baud rate generator (brg) can be configured and used as a basic 16-bit timer ? infrared data association (irda )-compliant infrared encoder/decoders, integrated with uart ? two enhanced 16-bit timers with capture, compare, and pwm capability ? watchdog timer (wdt) with de dicated internal rc oscillator ? on-chip debugger (ocd) ? optional 8-channel, 10-bit anal og-to-digital converter (adc) ? on-chip analog comparator ? up to 20 vectored interrupts ? direct led drive with prog rammable drive strengths ? voltage brown-out (vbo) protection ? power-on reset (por)
ps024315-1011 p r e l i m i n a r y part selection guide z8 encore! xp ? f0823 series product specification 2 ? 2.7 v to 3.6 v operating voltage ? up to thirteen 5 v-tolerant input pins ? 8-, 20-, and 28-pin packages ? 0c to +70c and ?40c to +105c for operating temperature ranges part selection guide table 1 lists the basic features and package styl es available for each de vice within the z8 encore! xp ? f0823 series product line. table 1. f0823 series family part selection guide part number flash (kb) ram (b) i/o adc inputs packages Z8F0823 8 1024 6?22 4?8 8-, 20-, and 28-pins z8f0813 8 1024 6?24 0 8-, 20-, and 28-pins z8f0423 4 1024 6?22 4?8 8-, 20-, and 28-pins z8f0413 4 1024 6?24 0 8-, 20-, and 28-pins z8f0223 2 512 6?22 4?8 8-, 20-, and 28-pins z8f0213 2 512 6?24 0 8-, 20-, and 28-pins z8f0123 1 256 6?22 4?8 8-, 20-, and 28-pins z8f0113 1 256 6?24 0 8-, 20-, and 28-pins
ps024315-1011 p r e l i m i n a r y block diagram z8 encore! xp ? f0823 series product specification 3 block diagram figure 1 displays a block diagram of the f0823 series architecture. figure 1. z8 encore! xp f0823 series block diagram gpio irda uart timers adc flash flash controller ram ram controller memory interrupt controller on-chip debugger ez8 cpu wdt por/vbo and reset controller register bus memory busses system clock comparator low power rc oscillator oscillator control internal precision oscillator
ps024315-1011 p r e l i m i n a r y cpu and peripheral overview z8 encore! xp ? f0823 series product specification 4 cpu and peripheral overview the ez8 cpu, zilog?s latest 8-bit central processing unit (cpu), meets the continuing demand for faster and code-efficient microcon trollers. the ez8 cpu executes a superset of the original z8 instruction se t. the ez8 cpu features include: ? direct register-to-register architecture allows each register to function as an accumulator, improving execution time and d ecreasing the required program memory ? software stack allows much greater dept h in subroutine calls and interrupts than hardware stacks ? compatible with existing z8 code ? expanded internal register file allows access of up to 4 kb ? new instructions improve execution efficiency for code developed using higher-level programming languages, including c ? pipelined instruction fetch and execution ? new instructions for improv ed performance including bit, bswap, btj, cpc, ldc, ldci, lea, mult, and srl ? new instructions support 12-bit linea r addressing of the register file ? up to 10 mips operation ? c-compiler friendly ? 2 to 9 clock cycles per instruction ? for more information about the ez8 cpu, refer to the ez8 cpu core user manual (um0128) available for download at www.zilog.com . general-purpose i/o f0823 series features 6 to 24 port pins (por ts a?c) for general-pu rpose i/o (gpio). the number of gpio pins available is a function of package. each pin is individually program- mable. 5 v-tolerant input pins are available on all i/os on 8-pin devices, most i/os on other package types. flash controller the flash controller programs and erases fl ash memory. the flash controller supports protection against accidental pr ogram and erasure, as well as factory serialization and read protection.
ps024315-1011 p r e l i m i n a r y cpu and peripheral overview z8 encore! xp ? f0823 series product specification 5 internal precision oscillator the internal precision oscillator (ipo) is a tr immable clock source that requires no exter- nal components. 10-bit analog-to- digital converter the optional analog-to-digital co nverter (adc) converts an analog input signal to a 10-bit binary number. the adc accepts inputs from eigh t different analog input pins in both sin- gle-ended and differential modes. analog comparator the analog comparator compares the signal at an input pin with either an internal pro- grammable voltage reference or a second input pin. the comparat or output can be used to drive either an output pin or to generate an interrupt. universal asynchronous receiver/transmitter the uart is full-duplex and capable of handling asynchronous data transfers. the uart supports 8- and 9-bit data modes and select able parity. the uart also supports multi- drop address processing in hardware. the uart baud rate generator can be configured and used as a basic 16-bit timer. timers two enhanced 16-bit reloadable timers can be used for timing/counting events or for motor control operations. these timers provid e a 16-bit programmable reload counter and operate in one-shot, continuous, gated, capture, capture restart, compare, capture and compare, pwm single output, and pwm dual output modes. interrupt controller z8 encore! xp ? f0823 series products support up to 20 interrupts. these interrupts con- sist of eight internal peripheral interrupts and 12 general-purpose i/o pin interrupt sources. the interrupts have three levels of programmable interrupt priority. reset controller z8 encore! xp ? f0823 series products ca n be reset using the reset pin, por, wdt time-out, stop mode exit, or voltage brown-out warning signal. the reset pin is bidi- rectional, that is, it func tions as reset source as well as a reset indicator.
ps024315-1011 p r e l i m i n a r y cpu and peripheral overview z8 encore! xp ? f0823 series product specification 6 on-chip debugger f0823 series products feature an integrated on-chip debugger. the ocd provides a rich- set of debugging capabilities, such as read ing and writing registers, programming flash memory, setting breakpoints and executing co de. a single-pin inte rface provides commu- nication to the ocd.
ps024315-1011 p r e l i m i n a r y pin description z8 encore! xp ? f0823 series product specification 7 pin description z8 encore! xp f0823 series products are available in a variety of package styles and pin configurations. this chapter describes the signals and pin configurations available for each of the package styles. for information about physical package specifications, see the packaging chapter on page 210 . available packages table 2 lists the package styles that are availa ble for each device in the f0823 series prod- uct line. pin configurations figures 2 through 4 display the pin configurations for all packages available in the f0823 series. for description of signals, see tabl e 3. the analog input alternate functions (anax ) are not available on the z8f0x13 devices. the analog supply pins (av dd and av ss ) are also not available on these pa rts, and are replaced by pb6 and pb7. at reset, all pins of ports a, b, and c defau lt to an input state. in addition, any alternate functionality is not enabled, so the pins fu nction as general-purpose input ports until pro- grammed otherwise. the pin configurations listed are preliminary and subject to change based on manufactur- ing limitations. table 2. f0823 series package options part number adc 8-pin pdip 8-pin soic 20-pin pdip 20-pin soic 20-pin ssop 28-pin pdip 28-pin soic 28-pin ssop 8-pin qfn/ mlf-s Z8F0823yesxxxxxxxx x z8f0813noxxxxxxxx x z8f0423yesxxxxxxxx x z8f0413noxxxxxxxx x z8f0223yesxxxxxxxx x z8f0213noxxxxxxxx x z8f0123yesxxxxxxxx x z8f0113noxxxxxxxx x
ps024315-1011 p r e l i m i n a r y pin configurations z8 encore! xp ? f0823 series product specification 8 figure 2. z8f08x3, z8f04x3, f02x3 and z8f01x3 in 8-pin soic, qfn/mlf-s, or pdip package* figure 3. z8f08x3, z8f04x3, f02x3 and z8f01x3 in 20-pin soic, ssop or pdip package* figure 4. z8f08x3, z8f04x3, f02x3 and z8f01x3 in 28-pin soic, ssop or pdip package* vss pa5/txd0/t1out /ana0/cinp pa4/rxd0/ana1/cinn pa3/cts0 /ana2/cout/t1in vdd pa0/t0in/t0out /dbg pa1/t0out/ana3/vref/clkin pa2/reset /de0/t1out 2 1 3 4 7 8 6 5 pb0/ana0 pc3/cout/led pc2/ana6/led/vref pc1/ana5/cinn/led pc0/ana4/cinp/led dbg reset pa7/t1out pa6/t1in/t1out pb1/ana1 pb2/ana2 pb3/clkin/ana3 vdd pa0/t0in/t0out pa1/t0out vss pa2/de0 1 pa5/txd0 pa3/cts0 5 10 pa4/rxd0 2 3 4 6 7 8 9 20 16 11 19 18 17 15 14 13 12 pb1/ana1 pb0/ana0 pc3/cout/led pc2/ana6/led pc1/ana5/cinn/led pc0/ana4/cinp/led dbg reset pc7/led pb2/ana2 pb3/clkin/ana3 pb4/ana7 pb5/vref (pb6) avdd vdd pa0/t0in/t0out pa1/t0out 1 pc6/led vss 5 10 (pb7) avss pa2/de0 pa3/cts0 pa4/rxd0 14 pa5/txd0 2 3 4 6 7 8 9 11 12 13 pc5/led pc4/led pa7/t1out pa6/t1in/t1out 28 24 19 15 27 26 25 23 22 21 20 18 17 16
ps024315-1011 p r e l i m i n a r y signal descriptions z8 encore! xp ? f0823 series product specification 9 * analog input alternate functions (ana) are not available on z8f0x13 devices. signal descriptions table 3 lists the z8 encore! xp f0823 series signals. to determine the signals available for the specific package styles, see the pin configurations section on page 7 . table 3. signal descriptions signal mnemonic i/o description general-purpose i/o ports a?d pa[7:0] i/o port a. these pins are used for general-purpose i/o. pb[7:0] 1 i/o port b. these pins are used for general-purpose i/o. pb6 and pb7 are available only in those devices without an adc. pc[7:0] i/o port c. these pins are used for general-purpose i/o. uart controllers txd0 o transmit data. this signal is the transmit output from the uart and irda. rxd0 i receive data. this signal is th e receive input for the uart and irda. cts0 i clear to send. this signal is th e flow control input for the uart. de o driver enable. this signal allows au tomatic control of external rs-485 drivers. this signal is approximat ely the inverse of the txe (transmit empty) bit in the uart status 0 re gister. the de signal can be used to ensure the external rs-485 driver is enabled when data is transmitted by the uart. timers t0out/t1out o timer output 0?1. these signals are output from the timers. t0out /t1out o timer complement output 0?1. these signals are output from the timers in pwm dual output mode. t0in/t1in i timer input 0?1. these signals are used as the capture, gating and coun- ter inputs. the t0in signal is multiplexed t0out signals. comparator cinp/cinn i comparator inputs. these signals are the positive and negative inputs to the comparator. notes: 1. pb6 and pb7 are only available in 28-pin packages wi thout adc. in 28-pin packages with adc, they are replaced by av dd and av ss . 2. the av dd and av ss signals are available only in 28-pin packages with adc. they are replaced by pb6 and pb7 on 28-pin packages without adc. note:
ps024315-1011 p r e l i m i n a r y signal descriptions z8 encore! xp ? f0823 series product specification 10 cout o comparator output. this is the output of the comparator. analog ana[7:0] i analog port. these signals are used as inputs to the adc. the ana0, ana1, and ana2 pins can also access the inputs and output of the inte- grated transimpedance amplifier. vref i/o analog-to-digital converter reference voltage input. clock input clkin i clock input signal. this pin can be used to input a ttl-level signal to be used as the system clock. led drivers led o direct led drive capability. all port c pins have the capability to drive an led without any other external components. these pins have programma- ble drive strengths set by the gpio block. on-chip debugger dbg i/o debug. this signal is the control and data input and output to and from the ocd. caution: the dbg pin is open-drain and requires an external pull-up resistor to ensure proper operation. reset reset i/o reset. generates a reset when assert ed (driven low). also serves as a reset indicator; the z8 en core! xp forces this pin low when in reset. this pin is open-drain and features an enabled internal pull-up resistor. power supply v dd i digital power supply. av dd 2 i analog power supply. v ss i digital ground. av ss i analog ground. table 3. signal descriptions (continued) signal mnemonic i/o description notes: 1. pb6 and pb7 are only available in 28-pin packages wi thout adc. in 28-pin packages with adc, they are replaced by av dd and av ss . 2. the av dd and av ss signals are available only in 28-pin packages with adc. they are replaced by pb6 and pb7 on 28-pin packages without adc.
ps024315-1011 p r e l i m i n a r y pin characteristics z8 encore! xp ? f0823 series product specification 11 pin characteristics table 4 provides detailed info rmation about the characteristics for each pin available on z8 encore! xp f0823 series 20- and 28-pin de vices. data in table 4 is sorted alphabeti- cally by the pin symbol mnemonic. all six i/o pins on the 8-pin packages are 5 v-tolerant (unless the pull-up devices are enabled). the right-most column in table 4 d escribes 5 v tolerance fo r the 20- and 28-pin packages only. table 4. pin characteristics (20- and 28-pin devices)* symbol mnemonic direction reset direction active low or active high tristate output internal pull-up or pull- down schmitt- trigger input open drain output 5 v tolerance avdd n/a n/a n/a n/a n/a n/a n/a n/a avss n/a n/a n/a n/a n/a n/a n/a na dbg i/o i n/a yes no yes yes yes pa[7:0] i/o i n/a yes program- mable pull-up yes yes, programmable pa[7:2] only pb[7:0] i/o i n/a yes program- mable pull-up yes yes, programmable pb[7:6] only pc[7:0] i/o i n/a yes program- mable pull-up yes yes, programmable pc[7:3] only reset i/o i/o (defaults to reset ) low (in reset mode) yes (pd0 only) always on for reset yes always on for reset yes vdd n/a n/a n/a n/a n/a n/a vss n/a n/a n/a n/a n/a n/a note: pb6 and pb7 are available only in the devices without adc. note:
ps024315-1011 p r e l i m i n a r y pin characteristics z8 encore! xp ? f0823 series product specification 12 table 5 provides detailed info rmation about the characteristics for each pin available on z8 encore! xp f0823 series 8-pin devices. table 5. pin characteristics (8-pin devices) symbol mnemonic direction reset direction active low or active high tristate output internal pull-up or pull- down schmitt- trigger input open drain output 5 v tolerance pa0/dbg i/o i (but can change during reset if key sequence detected) n/a yes program- mable pull-up yes yes, programmable yes, unless pull-ups enabled pa1 i/o i n/a yes program- mable pull-up yes yes, programmable yes, unless pull-ups enabled reset /pa2 i/o i/o (defaults to reset ) n/a yes program- mable for pa2; always on for reset yes programma- ble for pa2; always on for reset yes, unless pull-ups enabled pa[5:3] i/o i n/a yes program- mable pull-up yes yes, programmable yes, unless pull-ups enabled vdd n/a n/a n/a n/a n/a n/a n/a n/a vss n/a n/a n/a n/a n/a n/a n/a n/a
ps024315-1011 p r e l i m i n a r y address space z8 encore! xp ? f0823 series product specification 13 address space the ez8 cpu can access three distinct address spaces: ? the register file contains addresses for the general-purpose registers and the ez8 cpu, peripheral, and general-purp ose i/o port control registers ? the program memory contains addresses for all memory locations having executable code and/or data ? the data memory contains addresses for all memory locations that contain data only ? these three address spaces are covered brie fly in the following subsections. for more detailed information regarding the ez8 cp u and its address space, refer to the ez8 cpu core user manual (um0128) , available for download at www.zilog.com . register file the register file address space in the z8 encore! xp ? mcu is 4 kb (4096 bytes). the register file is composed of two sections: co ntrol registers and general-purpose registers. when instructions are executed, registers defined as sources are read, and registers defined as destinations are written. the architecture of the ez8 cpu allows all general-purpose registers to function as accumulators, address pointers, index registers, stack areas, or scratch pad memory. the upper 256 bytes of the 4 kb register file address space are reserved for control of the ez8 cpu, the on-chip peripherals, and the i/o ports. these registers are located at addresses from f00h to fffh . some of the addresses within the 256 b control register section are reserved (unavailable). reading fro m a reserved register file address returns an undefined value. writing to reserved register file addr esses is not recommended and can produce unpredictable results. the on-chip ram always begins at address 000h in the register file address space. z8 encore! xp f0823 series devices contain 256 b?1 kb of on-chip ram. reading from register file addresses outside the availabl e ram addresses (and not within the control register address space) returns an undefined va lue. writing to these register file addresses produces no effect. program memory the ez8 cpu supports 64 kb of program me mory address space. f0823 series devices contain 1 kb to 8 kb of on-chip flash memo ry in the program memory address space. reading from program memory addresses outside the available flash memory addresses
ps024315-1011 p r e l i m i n a r y program memory z8 encore! xp ? f0823 series product specification 14 returns ffh . writing to these unimplemented prog ram memory addresses produces no effect. table 6 describes the program memory maps for the z8 encore! xp f0823 series products. table 6. z8 encore! xp f0823 series program memory maps program memory address (hex) function Z8F0823 and z8f0813 products 0000?0001 flash option bits 0002?0003 reset vector 0004?0005 wdt interrupt vector 0006?0007 illegal instruction trap 0008?0037 interrupt vectors* 0038?003d oscillator fail traps* 003e?0fff program memory z8f0423 and z8f0413 products 0000?0001 flash option bits 0002?0003 reset vector 0004?0005 wdt interrupt vector 0006?0007 illegal instruction trap 0008?0037 interrupt vectors* 0038?003d oscillator fail traps* 003e?0fff program memory z8f0223 and z8f0213 products 0000?0001 flash option bits 0002?0003 reset vector 0004?0005 wdt interrupt vector 0006?0007 illegal instruction trap 0008?0037 interrupt vectors* 0038?003d oscillator fail traps* 003e?07ff program memory note: *see the trap and interrupt vectors in order of priority section on page 55 for a list of the interrupt vectors and traps.
ps024315-1011 p r e l i m i n a r y data memory z8 encore! xp ? f0823 series product specification 15 data memory z8 encore! xp f0823 series does not use the ez8 cpu?s 64 kb data memory address space. flash information area table 7 lists the f0823 series flash informa tion area. this 128 b information area is accessed by setting bit 7 of the flash page se lect register to 1. when access is enabled, the flash information area is mapped into the program me mory and overlays the 128 bytes at addresses fe00h to ff7fh . when the information area access is enabled, all reads from these program memory addresses retu rn the information area data rather than the program memory data. access to the flash information area is read-only. z8f0123 and z8f0113 products 0000?0001 flash option bits 0002?0003 reset vector 0004?0005 wdt interrupt vector 0006?0007 illegal instruction trap 0008?0037 interrupt vectors* 0038?003d oscillator fail traps* 003e?03ff program memory table 7. f0823 series flash memory information area map program memory address (hex) function fe00?fe3f zilog option bits. fe40?fe53 part number. 20-character ascii alphanumeric code left-justified and filled with fh. fe54?fe5f reserved. fe60?fe7f zilog calibration data. fe80?ffff reserved. table 6. z8 encore! xp f0823 series program memory maps (continued) program memory address (hex) function note: *see the trap and interrupt vectors in order of priority section on page 55 for a list of the interrupt vectors and traps.
ps024315-1011 p r e l i m i n a r y register map z8 encore! xp ? f0823 series product specification 16 register map table 8 lists an address map of the z8 enco re! xp f0823 series register file. not all devices and package styl es in the z8 encore! xp f0823 series support the adc, nor all gpio ports. consider registers for un implemented peripherals to be reserved. table 8. register file address map address (hex) register description mnemonic reset (hex) page no. general-purpose ram Z8F0823/z8f0813 devices 000?3ff general-purpose register file ram ? xx 400?eff reserved ? xx z8f0423/z8f0413 devices 000?3ff general-purpose register file ram ? xx 400?eff reserved ? xx z8f0223/z8f0213 devices 000?1ff general-purpose register file ram ? xx 200?eff reserved ? xx z8f0123/z8f0113 devices 000?0ff general-purpose register file ram ? xx 100?eff reserved ? xx timer 0 f00 timer 0 high byte t0h 00 84 f01 timer 0 low byte t0l 01 84 f02 timer 0 reload high byte t0rh ff 85 f03 timer 0 reload low byte t0rl ff 85 f04 timer 0 pwm high byte t0pwmh 00 86 f05 timer 0 pwm low byte t0pwml 00 86 f06 timer 0 control 0 t0ctl0 00 87 f07 timer 0 control 1 t0ctl1 00 88 timer 1 f08 timer 1 high byte t1h 00 84 f09 timer 1 low byte t1l 01 84 note: xx = undefined.
ps024315-1011 p r e l i m i n a r y register map z8 encore! xp ? f0823 series product specification 17 timer 1 (cont?d) f0a timer 1 reload high byte t1rh ff 85 f0b timer 1 reload low byte t1rl ff 85 f0c timer 1 pwm high byte t1pwmh 00 86 f0d timer 1 pwm low byte t1pwml 00 86 f0e timer 1 control 0 t1ctl0 00 87 f0f timer 1 control 1 t1ctl1 00 84 f10?f3f reserved ? xx uart f40 uart0 transmit data u0txd xx 109 uart0 receive data u0rxd xx 109 f41 uart0 status 0 u0stat0 0000011xb 110 f42 uart0 control 0 u0ctl0 00 112 f43 uart0 control 1 u0ctl1 00 112 f44 uart0 status 1 u0stat1 00 111 f45 uart0 address compare u0addr 00 115 f46 uart0 baud rate high byte u0brh ff 115 f47 uart0 baud rate low byte u0brl ff 115 f48?f6f reserved ? xx analog-to-digital converter (adc) f70 adc control 0 adcctl0 00 127 f71 adc control 1 adcctl1 80 127 f72 adc data high byte adcd_h xx 130 f73 adc data low bits adcd_l xx 130 f74?f7f reserved ? xx low power control f80 power control 0 pwrctl0 80 32 f81 reserved ? xx led controller f82 led drive enable leden 00 51 f83 led drive level high byte ledlvlh 00 52 table 8. register file address map (continued) address (hex) register description mnemonic reset (hex) page no. note: xx = undefined.
ps024315-1011 p r e l i m i n a r y register map z8 encore! xp ? f0823 series product specification 18 led controller (cont?d) f84 led drive level low byte ledlvll 00 53 f85 reserved ? xx oscillator control f86 oscillator control oscctl a0 172 f87?f8f reserved ? xx comparator 0 f90 comparator 0 control cmp0 14 133 f91?fbf reserved ? xx interrupt controller fc0 interrupt request 0 irq0 00 59 fc1 irq0 enable high bit irq0enh 00 62 fc2 irq0 enable low bit irq0enl 00 62 fc3 interrupt request 1 irq1 00 60 fc4 irq1 enable high bit irq1enh 00 64 fc5 irq1 enable low bit irq1enl 00 64 fc6 interrupt request 2 irq2 00 61 fc7 irq2 enable high bit irq2enh 00 65 fc8 irq2 enable low bit irq2enl 00 66 fc9?fcc reserved ? xx fcd interrupt edge select irqes 00 67 fce shared interrupt select irqss 00 67 fcf interrupt control irqctl 00 68 gpio port a fd0 port a address paaddr 00 40 fd1 port a control pactl 00 42 fd2 port a input data pain xx 43 fd3 port a output data paout 00 43 gpio port b fd4 port b address pbaddr 00 40 fd5 port b control pbctl 00 42 table 8. register file address map (continued) address (hex) register description mnemonic reset (hex) page no. note: xx = undefined.
ps024315-1011 p r e l i m i n a r y register map z8 encore! xp ? f0823 series product specification 19 gpio port b (cont?d) fd6 port b input data pbin xx 43 fd7 port b output data pbout 00 43 gpio port c fd8 port c address pcaddr 00 40 fd9 port c control pcctl 00 42 fda port c input data pcin xx 43 fdb port c output data pcout 00 43 fdc?fef reserved ? xx watchdog timer (wdt) ff0 reset status rststat xx 94 watchdog timer control wdtctl xx 94 ff1 watchdog timer reload upper byte wdtu ff 95 ff2 watchdog timer reload high byte wdth ff 95 ff3 watchdog timer reload low byte wdtl ff 95 ff4?ff5 reserved ? xx trim bit control ff6 trim bit address trmadr 00 148 ff7 trim data trmdr xx 149 flash memory controller ff8 flash control fctl 00 141 ff8 flash status fstat 00 142 ff9 flash page select fps 00 143 flash sector protect fprot 00 144 ffa flash programming frequency high byte ffreqh 00 145 ffb flash programming frequency low byte ffreql 00 145 table 8. register file address map (continued) address (hex) register description mnemonic reset (hex) page no. note: xx = undefined.
ps024315-1011 p r e l i m i n a r y register map z8 encore! xp ? f0823 series product specification 20 ez8 cpu ffc flags ? xx refer to the ez8 cpu core user man- ual (um01 28) ffd register pointer rp xx ffe stack pointer high byte sph xx fff stack pointer low byte spl xx table 8. register file address map (continued) address (hex) register description mnemonic reset (hex) page no. note: xx = undefined.
ps024315-1011 p r e l i m i n a r y reset and stop mode recovery z8 encore! xp ? f0823 series product specification 21 reset and stop mode recovery the reset controller within the z8 encore! xp f0823 series controls reset and stop mode recovery operation and provides indication of low su pply voltage conditions. in typical operation, the following events cause a reset: ? power-on reset (por) ? voltage brown-out (vbo) ? watchdog timer time-out (when configured by the wdt_res flash option bit to initiate a reset) ? external reset pin assertion (when the alternate reset function is enabled by the gpio register) ? on-chip debugger initiated reset (ocdctl[0] set to 1) ? when the device is in stop mode, a st op mode reco very is initiated by either of the fol- lowing: ? watchdog timer time-out ? gpio port input pin transition on an enabled stop mode recovery source ? the vbo circuitry on the device performs the follo wing function: ? generates the vbo reset when the supply voltage drops below a minimum safe level reset types f0823 series mcus provide several differen t types of reset operations. stop mode recovery is considered a form of reset. tabl e 9 lists the types of reset and their operating characteristics. the duration of a system reset is longer if the external crystal oscillator is enabled by the flash option bits; this configuration allows additional time for oscillator startup. table 9. reset and stop mode recovery characteristics and latency reset type reset characteristics and latency control registers ez8 cpu reset latency (delay) system reset reset (as applicable) reset 66 internal precision oscillator cycles stop mode recovery unaffected, except wdt_ctl and osc_ctl registers reset 66 internal precision oscillator cycles + ipo startup time
ps024315-1011 p r e l i m i n a r y reset types z8 encore! xp ? f0823 series product specification 22 during a system reset or stop mode recovery, the ipo requires 4 s to start up. then the z8 encore! xp f0823 series device is held in reset for 66 cycles of the internal precision oscillator. if the crystal oscillator is enabled in the flash option bits, this reset period is increased to 5000 ipo cycles. when a reset oc curs because of a low voltage condition or power-on reset, this delay is measured from the time that the supply voltage first exceeds the por level. if the external pin reset remain s asserted at the end of the reset period, the device remains in reset until the pin is deasserted. at the beginning of reset, all gpio pins are co nfigured as inputs with pull-up resistor dis- abled. during reset, the ez8 cpu and on-chip peripher als are idle; however, the on-chip crystal oscillator and watchdog timer oscillator continue to run. upon reset, control registers w ithin the register file that have a defined reset value are loaded with their reset values. other control registers (including the stack pointer, regis- ter pointer, and flags) and general-purpo se ram are undefined following reset. the ez8 cpu fetches the reset vector at program memory addresses 0002h and 0003h and loads that value into the program counter. prog ram execution begins at the reset vector address. when the control registers are re-initialized by a system reset, the system clock after reset is always the ipo. the software must reconfig ure the oscillator control block, such that the correct system clock source is enabled and selected.
ps024315-1011 p r e l i m i n a r y reset sources z8 encore! xp ? f0823 series product specification 23 reset sources table 10 lists the possible sources of a system reset. power-on reset each device in the z8 encore! xp f0823 series contains an internal por circuit. the por circuit monitors the supply voltage and holds the device in the reset state until the supply voltage reaches a safe operating level. after the supply voltage exceeds the por voltage threshold (v por ), the device is held in the r eset state until the por counter has timed out. if the crystal oscillator is enable d by the option bits, this time-out is longer. after the z8 encore! xp f0823 series device ex its the por state, the ez8 cpu fetches the reset vector. following the por, the por status bit in watchdog timer control (wdtctl) register is set to 1. figure 5 displays por operation. for the por threshold voltage (v por ), see the electri- cal characteristics chapter on page 196. table 10. reset sources and resulting reset type operating mode reset source special conditions normal or halt modes power-on reset/voltage brown- out. reset delay begins after supply voltage exceeds por level. watchdog timer time-out when configured for reset. none. reset pin assertion. all reset pulses less than three system clocks in width are ignored. ocd initiated reset (ocdctl[0] set to 1). system reset, except the ocd is unaffected by the reset. stop mode power-on reset/voltage brown- out. reset delay begins after supply voltage exceeds por level. reset pin assertion. all reset pulses less than the specified analog delay are ignored. see the electrical characteris- tics chapter on page 196 . dbg pin driven low. none.
ps024315-1011 p r e l i m i n a r y reset sources z8 encore! xp ? f0823 series product specification 24 voltage brown-out reset the devices in the z8 encore! xp f0823 se ries provide low vbo protection. the vbo circuit senses when the supply voltage drops to an unsafe level (below the vbo threshold ? voltage) and forces the device into the reset state. while the supply voltage remains below the por voltage threshold (v por ), the vbo block holds the device in the reset. after the supply voltage again exceeds the power-on reset voltage threshold, the device progresses through a full system reset sequence, as described in the power-on reset sec- tion on page 23. following por, the por stat us bit in the reset status (rststat) regis- ter is set to 1. figure 6 displays voltag e brown-out operation. for the vbo and por threshold voltages (v vbo and v por ), see the electrical characteristics chapter on page 196. the vbo circuit can be either enabled or disabled during stop mode. operation during stop mode is set by the vbo_ao flash optio n bit. for information about configuring vbo_ao, see the flash option bits chapter on page 146. figure 5. power-on reset operation v cc = 0.0v v cc = 3.3 v v por v vbo internal precision internal reset signal program execution por counter delay oscillator note: not to scale
ps024315-1011 p r e l i m i n a r y reset sources z8 encore! xp ? f0823 series product specification 25 the por level is greater than the vbo leve l by the specified hysteresis value. this ensures that the device undergoes a po r after recovering from a vbo condition. watchdog timer reset if the device is in normal or stop mode, the watchdog timer can initiate a system reset at time-out if the wdt_res flash option bit is programmed to 1. this is the unprogrammed state of the wdt_res flash option bit. if the bit is programmed to 0, it configures the watchdog timer to cause an interrupt, not a system reset, at time-out. the wdt status bit in the wdt control register is set to signify th at the reset was initi- ated by the watchdog timer. external reset input the reset pin has a schmitt-triggered input and an internal pull-up resistor. once the reset pin is asserted for a minimum of four sy stem clock cycles, th e device progresses through the system reset sequence. because of the possible asynchronicity of the system figure 6. voltage brown-out reset operation v cc = 3.3 v v por v vbo internal reset signal program execution program execution voltage brown-out v cc = 3.3 v system clock wdt clock por counter delay note: not to scale
ps024315-1011 p r e l i m i n a r y stop mode recovery z8 encore! xp ? f0823 series product specification 26 clock and reset signals, the required reset duration can be as short as three clock periods and as long as four. a reset pulse three clock cycles in duration might trigger a reset; a pulse four cycles in duration always triggers a reset. while the reset input pin is asserted low, the z8 encore! xp f0823 series devices remain in the reset state. if the reset pin is held low beyond the system reset time- out, the device exits the reset state on th e system clock rising edge following reset pin deassertion. following a system re set initiated by the external reset pin, the ext sta- tus bit in the wdt control (wdtctl) register is set to 1. external reset indicator during system reset or when en abled by the gpio logic (see the port a?c control reg- isters section on page 42 ), the reset pin functions as an open -drain (active low) reset mode indicator in addition to the input functi onality. this reset output feature allows an z8 encore! xp f0823 series device to reset othe r components to which it is connected, even if that reset is caused by internal so urces such as por, vbo, or wdt events. after an internal reset event occurs, the internal circu itry begins driving the reset pin low. the reset pin is held low by the internal circuitry until the appropriate delay listed in table 9 has elapsed. on-chip debugger initiated reset a por is initiated using the on -chip debugger by setting the rst bit in the ocd control register. the ocd block is not reset but the r est of the chip goes th rough a normal system reset. the rst bit automatically clears duri ng the system reset. following the system reset, the por bit in the reset status (rststat) register is set. stop mode recovery the device enters into stop mode when ez8 cpu executes a stop instruction. for more details about stop mode, see the low-power modes section on page 30 . during stop mode recovery, the cpu is held in reset for 66 ipo cycles if the crystal oscillator is dis- abled or 5000 cycles if it is enabled. the smr delay also included the time required to start up the ipo. stop mode recovery does not affect on-chi p registers other than the watchdog timer control register (wdtctl) and the oscillator control register (oscctl). after any stop mode recovery, the ipo is enabled and selected as the system clock. if another sys- tem clock source is required or ipo disabling is required, the stop mode recovery code must reconfigure the oscillator control block su ch that the correct system clock source is enabled and selected.
ps024315-1011 p r e l i m i n a r y stop mode recovery z8 encore! xp ? f0823 series product specification 27 the ez8 cpu fetches the reset vector at program memory addresses 0002h and 0003h and loads that value into the program counte r. program execution begins at the reset vec- tor address. following stop mode recovery, the stop bit in the watchdog timer control register is set to 1. table 11 lists the st op mode recovery sour ces and resulting actions. the section following the table provides more detailed information about each of the stop mode recovery sources. stop mode recovery using watchdog timer time-out if the watchdog timer times out during stop mode, the device undergoes a stop mode recovery sequence. in the watchdog timer control register, the wdt and stop bits are set to 1. if the watchdog timer is configured to generate an interrupt upon time-out and z8 encore! xp f0823 series device is configured to respond to interrupts, the ez8 cpu services the watchdog timer interrupt request following the normal stop mode recovery sequence. stop mode recovery using a gpio port pin transition each of the gpio port pins can be configured as a stop mode recovery input source. on any gpio pin enabled as a stop mode recove ry source, a change in the input pin value (from high to low or from low to high) initiates stop mode recovery. the smr pulses shorter than specified does not trigger a recovery. when this happens, the stop bit in the reset status (rststat) register is set to 1. in stop mode, the gpio port input data registers (pxin) are disabled. the port input data registers record the port transition only if the signal stays on the port pin through the end of the stop mode recovery delay. as a r esult, short pulses on the port pin can initiate stop mode recovery without being written to th e port input data regi ster or without ini- tiating an interrupt (if enabled for that pin). table 11. stop mode recovery sources and resulting action operating mode stop mode recovery source action stop mode watchdog timer time-out when configured for reset stop mode recovery watchdog timer time-out when configured for interrupt stop mode recovery followed by interrupt (if interrupts are enabled) data transition on any gpio port pin enabled as a stop mode recovery source stop mode recovery assertion of external reset pin system reset debug pin driven low system reset note: caution:
ps024315-1011 p r e l i m i n a r y reset register definitions z8 encore! xp ? f0823 series product specification 28 stop mode recovery using the external reset pin when a z8 encore! xp f0823 series device is in stop mode and the external reset pin is driven low, a system re set occurs. because of a glitch filter operating on the reset pin, the low pulse must be gr eater than the minimum width sp ecified, or it is ignored. for more details, see the electrical characteristics chapter on page 196. reset register definitions the following sections de fine the reset registers. reset status register the reset status (rststat) register is a read-o nly register that indicates the source of the most recent reset event, indicates a st op mode recovery ev ent, and indicates a watchdog timer time-out. reading this regi ster resets the upper four bits to 0. this register shares its address with the watchdog timer control register, which is write- only; see table 12. table 12. reset status register (rststat) bit 7 6 5 4 3 2 1 0 field por stop wdt ext reserved reset see descriptions in table 1300000 r/w rrrrrrrr address ff0h bit description [7] ? por power-on reset indicator if this bit is set to 1, a power-on reset event ha s occurred. this bit is re set to 0 if a wdt time- out or stop mode recovery occurs . this bit is also reset to 0 when the register is read. for por/stop mode recover event values, please see table 13. [6] ? stop stop mode recovery indicator if this bit is set to 1, a stop mode recovery is occurred. if the stop and wdt bits are both set to 1, the stop mode recovery occurred because of a wdt time-out. if the stop bit is 1 and the wdt bit is 0, the stop mode recovery was not caused by a wdt time-out. this bit is reset by a por or a wdt time-out that occurred while not in stop mode. reading this register also resets this bit. for por/stop mode recover event values, please see table 13. [5] ? wdt watchdog timer time-out indicator if this bit is set to 1, a wdt time-out has occu rred. a por resets this pin. a stop mode recov- ery from a change in an input pin also resets this bit. reading this register resets this bit; this read must occur before clearing the wdt interr upt. for por/stop mode recover event values, please see table 13.
ps024315-1011 p r e l i m i n a r y reset register definitions z8 encore! xp ? f0823 series product specification 29 [4] ? ext external reset indicator if this bit is set to 1, a reset initiated by the external reset pin occurred. a power-on reset or a stop mode recovery from a change in an in put pin resets this bit. reading this register resets this bit. for por/stop mode recover event values, please see table 13. [3:0] reserved these bits are reserved and must be programmed to 0000 when read. table 13. por indicator values reset or stop mode reco very event por stop wdt ext power-on reset 1000 reset using reset pin assertion 0001 reset using wdt time-out 0010 reset using the ocd (octctl[1] set to 1) 1000 reset from stop mode using dbg pin driven low1000 stop mode recovery using gpio pin transition 0100 stop mode recovery using wdt time-out 0110 bit description (continued)
ps024315-1011 p r e l i m i n a r y low-power modes z8 encore! xp ? f0823 series product specification 30 low-power modes z8 encore! xp f0823 series products contain power-saving features. the highest level of power reduction is provided by the stop mo de, in which nearly all device functions are powered down. the next lower level of powe r reduction is provided by the halt mode, in which the cpu is powered down. further power savings can be implemented by disabling individual peripheral blocks while in active mode (defined as being in neither stop nor halt mode). stop mode executing the ez8 cpu?s stop instruction places the device into stop mode, powering down all peripherals except the voltage brow n-out detector, and the watchdog timer. these two blocks may also be disabled for additional power savings. in stop mode, the operating characteristics are: ? primary crystal oscillator and internal precision oscillator are stopped; x in and x out (if previously enabled) are disabled, and pa 0/pa1 revert to the states programmed by the gpio registers ? system clock is stopped ? ez8 cpu is stopped ? program counter (pc) stops incrementing ? watchdog timer?s internal rc oscillator co ntinues to operate if enabled by the oscil- lator control register ? if enabled, the watchdog time r logic continues to operate ? if enabled for operation in stop mode by th e associated flash option bit, the voltage brown-out protection circuit continues to operate ? all other on-chip peripherals are idle ? to minimize current in stop mode, all gpio pins that are configured as digital inputs must be driven to one of the supply rails (v cc or gnd). additionally, any gpios config- ured as outputs must also be driven to one of the supply rails. the device can be brought out of stop mode using stop mode recove ry. for more information about stop mode recovery, see the reset and stop mode recovery chapter on page 21.
ps024315-1011 p r e l i m i n a r y halt mode z8 encore! xp ? f0823 series product specification 31 halt mode executing the ez8 cpu?s halt instructio n places the device into halt mode, which powers down the cpu but leaves all other peri pherals active. in halt mode, the operat- ing characteristics are: ? primary oscillator is enable d and continues to operate ? system clock is enabled and continues to operate ? ez8 cpu is stopped ? program counter st ops incrementing ? watchdog timer?s internal rc oscillator continues to operate ? if enabled, the watchdog ti mer continues to operate ? all other on-chip peripherals continue to operate ? the ez8 cpu can be brought out of halt mode by any of the following operations: ? interrupt ? watchdog timer time-out (interrupt or reset) ? power-on reset ? voltage brown-out reset ? external reset pin assertion ? to minimize current in halt mode, all gpio pins that are configured as inputs must be driven to one of the supply rails (v cc or gnd). peripheral-level power control in addition to the stop and halt modes, it is possible to disable each peripheral on each of the z8 encore! xp f0823 series devices. disabling a given peripheral minimizes its power consumption. power control register definitions the following sections describe the power control registers. power control register 0 each bit of the following registers disables a peripheral block, either by gating its system clock input or by removing power from the block.
ps024315-1011 p r e l i m i n a r y power control register definitions z8 encore! xp ? f0823 series product specification 32 this register is only reset during a power- on reset sequence. othe r system reset events do not affect it. table 14. power control register 0 (pwrctl0) bit 7 6 5 4 3 2 1 0 field reserved reserved vbo reserved adc comp reserved reset 10000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f80h bit description [7] reserved this bit is reserved and must be programmed to 1. [6:5] reserved these bits are reserved and must be programmed to 00. [4] ? vbo voltage brown-out detector disable this bit and the vbo_ao flash option bit must bo th enable the vbo for the vbo to be active. ? 0 = vbo enabled. ? 1 = vbo disabled. [3] reserved this bit is reserved and must be programmed to 0. [2] ? adc analog-to-digital converter disable 0 = analog-to-digital converter enabled. ? 1 = analog-to-digital converter disabled. [1] ? comp comparator disable 0 = comparator is enabled. ? 1 = comparator is disabled. [0] reserved this bit is reserved and must be programmed to 0. note:
ps024315-1011 p r e l i m i n a r y general-purpose input/output z8 encore! xp ? f0823 series product specification 33 general-purpose input/output z8 encore! xp f0823 series products support a maximum of 24 port pins (ports a?c) for general-purpose input/output (gpio) operations. each port contains control and data reg- isters. the gpio contro l registers determine data direction, open-drain, output drive cur- rent, programmable pull-ups, stop mode recovery functionality, and alternate pin functions. each port pin is individually programmable. in addition, the port c pins are capable of direct led drive at programmable drive strengths. gpio port availability by device table 15 lists the port pins availa ble with each device and package type. table 15. port availability by device and package type devices package 10-bit adc port a port b port c total i/o Z8F0823sb, Z8F0823pb z8f0423sb, z8f0423pb z8f0223sb, z8f0223pb z8f0123sb, z8f0123pb 8-pin yes [5:0] no no 6 z8f0813sb, z8f0813pb z8f0413sb, z8f0413pb z8f0213sb, z8f0213pb z8f0113sb, z8f011vpb 8-pin no [5:0] no no 6 Z8F0823ph, Z8F0823hh z8f0423ph, z8f0423hh z8f0223ph, z8f0223hh z8f0123ph, z8f0123hh 20-pin yes [7:0] [3:0] [3:0] 16 z8f0813ph, z8f0813hh z8f0413ph, z8f0413hh z8f0213ph, z8f0213hh z8f0113ph, z8f0113hh 20-pin no [7:0] [3:0] [3:0] 16 Z8F0823pj, Z8F0823sj z8f0423pj, z8f0423sj z8f0223pj, z8f0223sj z8f0123pj, z8f0123sj 28-pin yes [7:0] [5:0] [7:0] 22 z8f0813pj, z8f0813sj z8f0413pj, z8f0413sj z8f0213pj, z8f0213sj z8f0113pj, z8f0113sj 28-pin no [7:0] [7:0] [7:0] 24
ps024315-1011 p r e l i m i n a r y architecture z8 encore! xp ? f0823 series product specification 34 architecture figure 7 displays a simplified block diagram of a gpio port pin. in th is figure, the ability to accommodate alternate functions and variab le port current drive strength is not dis- played. gpio alternate functions many of the gpio port pins are used for general-purpose i/o and access to on-chip peripheral functions such as the timers and serial communication de vices. the port a?d alternate function subregisters configure these pins for either gpio or alternate function operation. when a pin is configured for alternate function, control of the port pin direction (input/output) is passed from the port a?d data direction registers to the alternate func- tion assigned to this pin. tables 16 and 17 list the alternate functions possible with each port pin for 8-pin and non-8-pin parts, respec tively. the alternate function associated at a pin is defined through alternate functio n sets subregisters afs1 and afs2. the crystal oscillator fu nctionality is not controlled by th e gpio block. when the crystal oscillator is enabled in the os cillator control block, the gpio functionality of pa0 and pa1 is overridden. in that case, th ose pins function as input and output for the crystal oscillator. figure 7. gpio port pin block diagram dq dq dq gnd vdd port output control port data direction port output data register port input data register port pin data bus system clock system clock schmitt-trigger
ps024315-1011 p r e l i m i n a r y gpio alternate functions z8 encore! xp ? f0823 series product specification 35 pa0 and pa6 contain two different timer functio ns, a timer input and a complementary timer output. both of these functions require the sa me gpio configuration, the selection between the two is based on the timer mode. for more details, see the timers chapter on page 69. for pins with multiple altern ate functions, zilog recommends writing to the afs1 and afs2 subregisters before enabling the altern ate function via the af subregister. this prevents spurious transitions throug h unwanted alternate function modes. table 16. port alternate function mapping (8-pin parts) port pin mnemonic alternate function description alternate function select register afs1 alternate function select register afs2 port a pa0 t0in timer 0 input afs1[0]: 0 afs2[0]: 0 reserved afs1[0]: 0 afs2[0]: 1 reserved afs1[0]: 1 afs2[0]: 0 t0out timer 0 output comp lement afs1[0]: 1 afs2[0]: 1 pa1 t0out timer 0 output afs1[1]: 0 afs2[1]: 0 reserved afs1[1]: 0 afs2[1]: 1 clkin external clock input afs1[1]: 1 afs2[1]: 0 analog functions* adc analog input/v ref afs1[1]: 1 afs2[1]: 1 pa2 de0 uart 0 driver enable afs1[2]: 0 afs2[2]: 0 reset external reset afs1[2]: 0 afs2[2]: 1 t1out timer 1 output afs1[2]: 1 afs2[2]: 0 reserved afs1[2]: 1 afs2[2]: 1 pa3 cts0 uart 0 clear to send afs1[3]: 0 afs2[3]: 0 cout comparator output afs1[3]: 0 afs2[3]: 1 t1in timer 1 input afs1[3]: 1 afs2[3]: 0 analog functions* adc analog input afs1[3]: 1 afs2[3]: 1 pa4 rxd0 uart 0 receive da ta afs1[4]: 0 afs2[4]: 0 reserved afs1[4]: 0 afs2[4]: 1 reserved afs1[4]: 1 afs2[4]: 0 analog functions* adc/comparator input (n) afs1[4]: 1 afs2[4]: 1 pa5 txd0 uart 0 transmit data afs1[5]: 0 afs2[5]: 0 t1out timer 1 output comp lement afs1[5]: 0 afs2[5]: 1 reserved afs1[5]: 1 afs2[5]: 0 analog functions* adc/comparator input (p) afs1[5]: 1 afs2[5]: 1 note: *analog functions include adc inputs, adc reference a nd comparator inputs. also, alternate function selection as described in the p ort a?c alternate function subregisters section on page 43 must be enabled. caution:
ps024315-1011 p r e l i m i n a r y gpio alternate functions z8 encore! xp ? f0823 series product specification 36 table 17. port alternate function mapping (non 8-pin parts) port pin mnemonic alternate function description alternate function set register afs1 port a 1 pa0 t0in/t0out timer 0 input/timer 0 output complement n/a reserved pa1 t0out timer 0 output reserved pa2 de0 uart 0 driver enable reserved pa3 cts0 uart 0 clear to send reserved pa4 rxd0/irrx0 uart 0 / irda 0 receive data reserved pa5 txd0/irtx0 uart 0 / irda 0 transmit data reserved pa6 t1in/t1out 2 timer 1 input/timer 1 output complement reserved pa7 t1out timer 1 output reserved notes: 1. because there is only a single alternate function for each port a pin, the alternate function set registers are not implemented for port a. enabling alternate function selections as described in the p ort a?c alternate function subregisters section on page 43 automatically enables the associated alternate function. 2. whether pa0/pa6 take on the timer input or timer out put complement function depends on the timer configura- tion as described in the timer pin signal operation section on page 83. 3. because there are at most two choice s of alternate function for any pin of port b, the alternate function set reg- ister afs2 is implemented but not used to select the fu nction. also, alternate function selection as described in the p ort a?c alternate function subregisters section on page 43 must also be enabled. 4. v ref is available on pb5 in 28-pin products only. 5. because there are at most two choices of alternate function for any pin of port c, the alternate function set reg- ister afs2 is implemented but not used to select the func tion. also, alternate function selection as described in the p ort a?c alternate function subregisters section on page 43 must also be enabled. 6. v ref is available on pc2 in 20-pin parts only.
ps024315-1011 p r e l i m i n a r y gpio alternate functions z8 encore! xp ? f0823 series product specification 37 port b 3 pb03 reserved afs1[0]: 0 ana0 adc analog input afs1[0]: 1 pb1 reserved afs1[1]: 0 ana1 adc analog input afs1[1]: 1 pb2 reserved afs1[2]: 0 ana2 adc analog input afs1[2]: 1 pb3 clkin external clock input afs1[3]: 0 ana3 adc analog input afs1[3]: 1 pb4 reserved afs1[4]: 0 ana7 adc analog input afs1[4]: 1 pb5 reserved afs1[5]: 0 v ref 4 adc voltage reference afs1[5]: 1 pb6 reserved afs1[6]: 0 reserved afs1[6]: 1 pb7 reserved afs1[7]: 0 reserved afs1[7]: 1 table 17. port alternate function mapping (non 8-pin parts) (continued) port pin mnemonic alternate function description alternate function set register afs1 notes: 1. because there is only a single alternate function for each port a pin, the alternate function set registers are not implemented for port a. enabling alternate function selections as described in the p ort a?c alternate function subregisters section on page 43 automatically enables the associated alternate function. 2. whether pa0/pa6 take on the timer input or timer out put complement function depends on the timer configura- tion as described in the timer pin signal operation section on page 83. 3. because there are at most two choice s of alternate function for any pin of port b, the alternate function set reg- ister afs2 is implemented but not used to select the fu nction. also, alternate function selection as described in the p ort a?c alternate function subregisters section on page 43 must also be enabled. 4. v ref is available on pb5 in 28-pin products only. 5. because there are at most two choices of alternate function for any pin of port c, the alternate function set reg- ister afs2 is implemented but not used to select the func tion. also, alternate function selection as described in the p ort a?c alternate function subregisters section on page 43 must also be enabled. 6. v ref is available on pc2 in 20-pin parts only.
ps024315-1011 p r e l i m i n a r y direct led drive z8 encore! xp ? f0823 series product specification 38 direct led drive the port c pins provide a current sinked output capable of driving an led without requir- ing an external resistor. the output sinks cu rrent at programmable levels of 3 ma, 7 ma, 13 ma, and 20 ma. this mode is enabled through the led control registers. the led drive enable (leden) register turns on th e drivers. the led drive level (ledlvlh and ledlvll) registers select the sink current. port c 4 pc0 reserved afs1[0]: 0 ana4/cinp adc or comparator input afs1[0]: 1 pc1 reserved afs1[1]: 0 ana5/cinn adc or comparator input afs1[1]: 1 pc2 reserved afs1[2]: 0 ana6/v ref 6 adc analog input or adc voltage refer- ence afs1[2]: 1 pc3 cout comparator output afs1[3]: 0 reserved afs1[3]: 1 pc4 reserved afs1[4]: 0 afs1[4]: 1 pc5 reserved afs1[5]: 0 afs1[5]: 1 pc6 reserved afs1[6]: 0 afs1[6]: 1 pc7 reserved afs1[7]: 0 afs1[7]: 1 table 17. port alternate function mapping (non 8-pin parts) (continued) port pin mnemonic alternate function description alternate function set register afs1 notes: 1. because there is only a single alternate function for each port a pin, the alternate function set registers are not implemented for port a. enabling alternate function selections as described in the p ort a?c alternate function subregisters section on page 43 automatically enables the associated alternate function. 2. whether pa0/pa6 take on the timer input or timer out put complement function depends on the timer configura- tion as described in the timer pin signal operation section on page 83. 3. because there are at most two choice s of alternate function for any pin of port b, the alternate function set reg- ister afs2 is implemented but not used to select the fu nction. also, alternate function selection as described in the p ort a?c alternate function subregisters section on page 43 must also be enabled. 4. v ref is available on pb5 in 28-pin products only. 5. because there are at most two choices of alternate function for any pin of port c, the alternate function set reg- ister afs2 is implemented but not used to select the func tion. also, alternate function selection as described in the p ort a?c alternate function subregisters section on page 43 must also be enabled. 6. v ref is available on pc2 in 20-pin parts only.
ps024315-1011 p r e l i m i n a r y shared reset pin z8 encore! xp ? f0823 series product specification 39 for correct operation, the led anode must be connected to v dd and the cathode must be connected to the gpio pin. us ing all port c pins in led drive mode with maximum cur- rent can result in excessive total current. fo r the maximum total current for the applicable package, see the electrical characteristics chapter on page 196. shared reset pin on the 8-pin product versions, the reset pin is shared with pa2, but the pin is not limited to output-only when in gpio mode. if pa2 on the 8-pin product is reconfigured as an input, ensure that no external stimulus drives the pin low during any reset sequence. because pa2 returns to its reset alternate function during system resets, driving it low holds th e chip in a reset state until the pin is released. shared debug pin on the 8-pin version of this device only, the debug pin shares function with the pa0 gpio pin. this pin performs as a general purpose input pin on power-up, but the debug logic monitors this pin during the reset sequence to determine if the unlock sequence occurs. if the unlock sequence is present, the debug func tion is unlocked and the pin no longer func- tions as a gpio pin. if it is not present, the debug feature is disabled until/unless another reset event occurs. for more details, see the on-chip debugger chapter on page 156. crystal oscillator override for systems using a crystal oscillator, pa0 and pa1 are used to connect the crystal. when the crystal oscillator is enabled (see the oscillator control register definitions section on page 171), the gpio settings are ove rridden and pa0 and pa1 are disabled. 5 v tolerance all six i/o pins on the 8-pin devices are 5 v-tolerant, unless the programmable pull-ups are enabled. if the pull-ups are en abled and inputs higher than v dd are applied to these parts, excessive current flows through thos e pull-up devices and can damage the chip. in the 20- and 28-pin versions of this devi ce, any pin which shares functionality with an adc, crystal or comparator port is not 5 v- tolerant, including pa [1:0], pb[5:0], and caution: note:
ps024315-1011 p r e l i m i n a r y external clock setup z8 encore! xp ? f0823 series product specification 40 pc[2:0]. all other signal pins are 5 v-tolerant, and can safely handle inputs higher than v dd even with the pull-ups enabled. external clock setup for systems using an external ttl drive, pb 3 is the clock source for 20- and 28-pin devices. in this case, configure pb3 for a lternate function clkin. write the oscillator control register (see the oscillator control register definitions section on page 171) such that the external oscillator is selected as the system clock. for 8-pin devices, use pa1 instead of pb3. gpio interrupts many of the gpio port pins are used as interrupt sources. some port pins are configured to generate an interrupt request on either the rising edge or falling edge of the pin input signal. other port pin interrupt sources generate an interrupt when any edge occurs (both rising and falling). for more information ab out interrupts using the gpio pins, see the i nterrupt c ontroller chapter on page 54. gpio control register definitions four registers for each port provide access to gpio control, input data, and output data. table 18 lists these port registers. use the port a?d address and control registers together to provide access to subregiste rs for port configuration and control. table 18. gpio port registers and subregisters port register mnemonic port register name p x addr port a?c address register (selects subregisters). p x ctl port a?c control register (p rovides access to subregisters). p x in port a?c input data register. p x out port a?c output data register. port subregister mnemonic port register name p x dd data direction. p x af alternate function. p x oc output control (open-drain).
ps024315-1011 p r e l i m i n a r y gpio control register definitions z8 encore! xp ? f0823 series product specification 41 port a?c address registers the port a?c address registers select the gpio port functionality accessible through the port a?c control registers. the port a?c ad dress and control regi sters combine to pro- vide access to all gpio port controls (table 19). p x hde high drive enable. p x smre stop mode recovery source enable. p x pue pull-up enable. pxafs1 alternate function set 1. pxafs2 alternate function set 2. table 19. port a?c gpio address registers (p x addr) bit 7 6 5 4 3 2 1 0 field paddr[7:0] reset 00h r/w r/wr/wr/wr/wr/wr/wr/wr/w address fd0h, fd4h, fd8h bit description [7:0] ? paddr port address the port address selects one of the subregisters accessible through the port control register. see table 20 for each subregister function. table 20. paddr[7:0] subregister functions paddr[7:0] port control subregister accessi ble using the port a?c control registers 00h no function. provides some protection against accidental port reconfiguration. 01h data direction. 02h alternate function. 03h output control (open-drain). 04h high drive enable. table 18. gpio port registers and subregisters (continued) port register mnemonic port register name
ps024315-1011 p r e l i m i n a r y gpio control register definitions z8 encore! xp ? f0823 series product specification 42 port a?c control registers the port a?c control registers set the gpio port operation. the value in the correspond- ing port a?c address register determines which subregister is read from or written to by a port a?c control register transaction; see table 21. 05h stop mode recove ry source enable. 06h pull-up enable. 07h alternate function set 1. 08h alternate function set 2. 09h?ffh no function. table 21. port a?c control registers (p x ctl) bit 7 6 5 4 3 2 1 0 field pctl reset 00h r/w r/wr/wr/wr/wr/wr/wr/wr/w address fd1h, fd5h, fd9h bit description [7:0] ? pctl port control the port control register provides access to all subregisters that configure the gpio port operation. table 20. paddr[7:0] subregister functions paddr[7:0] port control subregister accessi ble using the port a?c control registers
ps024315-1011 p r e l i m i n a r y gpio control register definitions z8 encore! xp ? f0823 series product specification 43 port a?c data dire ction subregisters the port a?c data direction subregister is accessed through the po rt a?c control regis- ter by writing 01h to the port a?c address register; see table 22. port a?c alternate fu nction subregisters the port a?c alternate function subregister (t able 23) is accessed through the port a?c control register by writing 02h to the port a?c address register. the port a?c alter- nate function subregisters enab le the alternate function selection on pins. if disabled, pins functions as gpio. if enabled, select one of four alternate functions using alternate func- tion set subregisters 1 and 2 as described in the the p ort a?c alternate function set 1 subregisters section on page 48 and the p ort a?c alternate function set 2 subregisters section on page 49. see the g pio alternate functions section on page 34 to determine the alternate function associated with each port pin. do not enable alternate functions for gpio po rt pins for which there is no associated al- ternate function. failure to follow this gu ideline can result in unpredictable operation. table 22. port a?c data di rection subregisters (pxdd) bit 7 6 5 4 3 2 1 0 field dd7 dd6 dd5 dd4 dd3 dd2 dd1 dd0 reset 11111111 r/w r/wr/wr/wr/wr/wr/wr/wr/w address if 01h in port a?c address register, accessi ble through the port a?c control register. bit description [7:0] ? ddx data direction these bits control the direction of the associated port pin. port alternate function operation overrides the data direction register setting. 0 = output. data in the port a?c output data register is driven onto the port pin. 1 = input. the port pin is sampled and the value written into the port a?c input data register. the output driver is tristated. note: x indicates the specific gpio port pin number (7?0). caution:
ps024315-1011 p r e l i m i n a r y gpio control register definitions z8 encore! xp ? f0823 series product specification 44 port a?c output c ontrol subregisters the port a?c output control subregister (t able 24) is accessed through the port a?c control register by writing 03h to the port a?c address register. setting the bits in the port a?c output control subregisters to 1 configures the specified port pins for open- drain operation. these subregisters affect the pi ns directly and, as a result, alternate func- tions are also affected. table 23. port a?c alternate function subregisters (pxaf) bit 7 6 5 4 3 2 1 0 field af7 af6 af5 af4 af3 af2 af1 af0 reset 00h (ports a?c); 04h (port a of 8-pin device) r/w r/w address if 02h in port a?c address register, access ible through the port a?c control register bit description [7:0] ? afx port alternate function enabled 0 = the port pin is in normal mode and the ddx bit in the port a?c da ta direction subregis- ter determines the direction of the pin. 1 = the alternate function selected through alte rnate function set subregisters is enabled. port pin operation is controlled by the alternate function. note: x indicates the specific gpio port pin number (7?0). table 24. port a?c output control subregisters (pxoc) bit 7 6 5 4 3 2 1 0 field poc7 poc6 poc5 poc4 poc3 poc2 poc1 poc0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address if 03h in port a?c address register, access ible through the port a?c control register bit description [7:0] ? pocx port output control these bits function independently of the altern ate function bit and always disable the drains if set to 1. 0 = the drains are enabled for any output mode (unless overridden by the alternate function). 1 = the drain of the associated pin is disabled (open-drain mode). note: x indicates the specific gpio port pin number (7?0).
ps024315-1011 p r e l i m i n a r y gpio control register definitions z8 encore! xp ? f0823 series product specification 45 port a?c high drive enable subregisters the port a?c high drive enable subregister (table 25) is accessed through the port a?c control register by writing 04h to the port a?c address register. setting the bits in the port a?c high drive enable subregisters to 1 configures the specified port pins for high- current output drive operation. the port a? c high drive enable subregister affects the pins directly and, as a result, alternate functions are also affected. table 25. port a?c high drive enable subregisters (phdex) bit 7 6 5 4 3 2 1 0 field phde7 phde6 phde5 phde4 phde3 phde2 phde1 phde0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address if 04h in port a?c address register, access ible through the port a?c control register bit description [7:0] ? phdex port high drive enabled. 0 = the port pin is configured for standard output current drive. 1 = the port pin is configured for high output current drive. note: x indicates the specific gpio port pin number (7?0).
ps024315-1011 p r e l i m i n a r y gpio control register definitions z8 encore! xp ? f0823 series product specification 46 port a?c stop mode recovery source enable subregisters the port a?c stop mode recovery source enable subregister (table 26) is accessed through the port a?c cont rol register by writing 05h to the port a?c address register. setting the bits in the port a? c stop mode recovery source en able subregisters to 1 con- figures the specified port pins as a stop mo de recovery source. during stop mode, any logic transition on a port pin enabled as a stop mode recovery source initiates stop mode recovery. table 26. port a?c stop mode recovery source enable subregisters (psmrex) bit 7 6 5 4 3 2 1 0 field psmre7 psmre6 psmre5 psmre4 psmre3 psmre2 psmre1 psmre0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address if 05h in port a?c address register, access ible through the port a?c control register bit description [7:0] ? psmrex port stop mode recovery source enabled. 0 = the port pin is not configured as a stop mode recovery source. transitions on this pin dur- ing stop mode do not initiate stop mode recovery. 1 = the port pin is configured as a stop mode recovery source. any logi c transition on this pin during stop mode initiates stop mode recovery. note: x indicates the specific gpio port pin number (7?0).
ps024315-1011 p r e l i m i n a r y gpio control register definitions z8 encore! xp ? f0823 series product specification 47 port a?c pull-up enable subregisters the port a?c pull-up enable subregister (t able 27) is accessed through the port a?c control register by writing 06h to the port a?c address register. setting the bits in the port a?c pull-up enable subregisters enable s a weak internal resi stive pull-up on the specified port pins. table 27. port a?c pull-up en able subregisters (ppuex) bit 7 6 5 4 3 2 1 0 field ppue7 ppue6 ppue5 ppue4 ppue3 ppue2 ppue1 ppue0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address if 06h in port a ? c address register, accessible through the port a ? c control register bit description [7:0] ? ppuex port pull-up enabled 0 = the weak pull-up on the port pin is disabled. 1 = the weak pull-up on the port pin is enabled. note: x indicates the specific gpio port pin number (7?0).
ps024315-1011 p r e l i m i n a r y gpio control register definitions z8 encore! xp ? f0823 series product specification 48 port a?c alternate func tion set 1 subregisters the port a?c alternate function set1 subregis ter (table 28) is accessed through the port a?c control register by writing 07h to the port a?c addres s register. the alternate function set 1 subregisters selects the alternate function available at a port pin. alternate functions selected by setting or clearing bits of this register are defined in ?gpio alter- nate functions? on page 34 . alternate function selection on port pins must also be enabled as described in the p ort a? c alternate function subregisters section on page 43. table 28. port a?c alternate function set 1 subregisters (pafs1x) bit 7 6 5 4 3 2 1 0 field pafs17 pafs16 pafs15 pafs14 pafs13 pafs12 pafs11 pafs10 reset 00h (all ports of 20/28 pin devices); 04h (port a of 8-pin device) r/w r/wr/wr/wr/wr/wr/wr/wr/w address if 07h in port a?c address register, access ible through the port a?c control register bit description [7:0] ? pafs1x port alternate function set to 1 0 = port alternate function selected as defined in table 15 (see the g pio alternate functions section on page 34). 1 = port alternate function selected as defined in table 15 (see the g pio alternate functions section on page 34). note: x indicates the specific gpio port pin number (7?0). note:
ps024315-1011 p r e l i m i n a r y gpio control register definitions z8 encore! xp ? f0823 series product specification 49 port a?c alternate func tion set 2 subregisters the port a?c alternate function set 2 subregis ter (table 29) is accessed through the port a?c control register by writing 08h to the port a?c addres s register. the alternate function set 2 subregisters selects the alternate function available at a port pin. alternate functions selected by setting or clearing bits of this register is defined in table 15 in the section the g pio alternate functions section on page 34. table 29. port a?c alternate function set 2 subregisters (pxafs2) bit 7 6 5 4 3 2 1 0 field pafs27 pafs26 pafs25 pafs24 pafs23 pafs22 pafs21 pafs20 reset 00h (all ports of 20/28 pin devices); 04h (port a of 8-pin device) r/w r/wr/wr/wr/wr/wr/wr/wr/w address if 08h in port a?c address register, access ible through the port a?c control register bit description [7:0] ? pafs2x port alternate function set 2 0 = port alternate function selected as defined in table 15 on page 33; also see the g pio alternate functions section on page 34). 1 = port alternate function selected as defined in table 15. note: x indicates the specific gpio port pin number (7?0).
ps024315-1011 p r e l i m i n a r y gpio control register definitions z8 encore! xp ? f0823 series product specification 50 port a?c input data registers reading from the port a?c input data registers (table 30 ) returns the sampled values from the corresponding port pi ns. the port a?c input data registers are read-only. the value returned for any unused ports is 0. unused ports include those missing on the 8- and 28-pin packages, as well as those missing on the adc-enabled 28-pin packages. table 30. port a?c input data registers (pxin) bit 7 6 5 4 3 2 1 0 field pin7 pin6 pin5 pin4 pin3 pin2 pin1 pin0 reset xxxxxxxx r/w rrrrrrrr address fd2h, fd6h, fdah bit description [7:0] ? pxin port input data sampled data from the corresponding port pin input. 0 = input data is logical 0 (low). 1 = input data is logical 1 (high). note: x indicates the specific gpio port pin number (7?0).
ps024315-1011 p r e l i m i n a r y gpio control register definitions z8 encore! xp ? f0823 series product specification 51 port a?c output data register the port a?c output data register (table 31) controls the output data to the pins. led drive enable register the led drive enable register, shown in tabl e 32, activates the controlled current drive. the alternate function register has no control over the led function; therefore, setting the alternate function register to select th e led function is not required. leden bits [7:0] correspond to port c bits [7:0], respectively. table 31. port a?c output data register (pxout) bit 7 6 5 4 3 2 1 0 field pout7 pout6 pout5 pout4 pout3 pout2 pout1 pout0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address fd3h, fd7h, fdbh bit description [7:0] ? pxout port output data these bits contain the data to be driven to the po rt pins. the values are only driven if the corre- sponding pin is configured as an output and t he pin is not configured for alternate function operation. 0 = drive a logical 0 (low). 1 = drive a logical 1 (high). high value is not driven if the drain has been disabled by setting the corresponding port output control register bit to 1. note: x indicates the specific gpio port pin number (7?0). table 32. led drive enable (leden) bit 7 6 5 4 3 2 1 0 field leden[7:0] reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f82h bit description [7:0] ? leden led drive enable these bits determine which port c pins are connected to an internal current sink. 0 = tristate the port c pin. 1= connect controlled current sink to the port c pin.
ps024315-1011 p r e l i m i n a r y gpio control register definitions z8 encore! xp ? f0823 series product specification 52 led drive level high register the led drive level registers contain two cont rol bits for each port c pin (table 33). these two bits select between four programmab le drive levels. each pin is individually programmable. table 33. led drive level high register (ledlvlh) bit 7 6 5 4 3 2 1 0 field ledlvlh[7:0] reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f83h bit description [7:0] ? ledlvlh led level high bit {ledlvlh, ledlvll} select one of four prog rammable current drive levels for each port c pin. 00 = 3 ma. 01= 7 ma. 10= 13 ma. 11= 20 ma.
ps024315-1011 p r e l i m i n a r y gpio control register definitions z8 encore! xp ? f0823 series product specification 53 led drive level low register the led drive level registers contain two cont rol bits for each port c pin (table 34). these two bits select between four programmab le drive levels. each pin is individually programmable. table 34. led drive level low register (ledlvll) bit 7 6 5 4 3 2 1 0 field ledlvll[7:0] reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f84h bit description [7:0] ? ledlvll led level high bit {ledlvlh, ledlvll} select one of four programmable current drive levels for each port c pin. 00 = 3 ma. 01 = 7 ma. 10 = 13 ma. 11 = 20 ma.
ps024315-1011 p r e l i m i n a r y interrupt controller z8 encore! xp ? f0823 series product specification 54 interrupt controller the interrupt controller on the z8 encore! xp f0823 series products prioritizes the inter- rupt requests from the on-chip peripherals and the gpio port pins. the features of inter- rupt controller include: ? 20 unique interrupt vectors ? 12 gpio port pin interrupt sources (two are shared) ? 8 on-chip peripheral interrupt sources (two are shared) ? ? flexible gpio interrupts ? eight selectable rising and falling edge gpio interrupts ? four dual-edge interrupts ? ? three levels of individually programmable interrupt priority ? watchdog timer can be configur ed to generate an interrupt ? interrupt requests (irqs) allow peripheral devi ces to suspend cpu oper ation in an orderly manner and force the cpu to start an interrupt service routine (isr). usually this interrupt service routine is involved with the exchange of data, status information, or control infor- mation between the cpu and the interrupting pe ripheral. when the service routine is com- pleted, the cpu returns to the operation from wh ich it was interrupted. the ez8 cpu supports both vectored and polled interrupt handling. for polled interrupts, the interrupt controller has no effect on ope ration. for more inform ation about interrupt servicing by the ez8 cpu, refer to the ez8 cpu core user manual (um0128) available for download at www.zilog.com . interrupt vector listing table 35 lists all of the interrupts available in order of priority. the interrupt vector is stored with the most-significant byte (msb) at the even program memory address and the least-significant byte (lsb) at the following odd program memory address. some port interrupts are not av ailable on the 8- and 20-pin packages. the adc interrupt is unavailable on devices not containing an adc. note:
ps024315-1011 p r e l i m i n a r y interrupt vector listing z8 encore! xp ? f0823 series product specification 55 table 35. trap and interrupt vectors in order of priority priority program memory ? vector address interrupt or trap source highest 0002h reset (not an interrupt) 0004h watchdog timer (see the watchdog timer section on page 91) 003ah primary oscillator fa il trap (not an interrupt) 003ch watchdog timer oscillator fail trap (not an interrupt) 0006h illegal instruction trap (not an interrupt) 0008h reserved 000ah timer 1 000ch timer 0 000eh uart 0 receiver 0010h uart 0 transmitter 0012h reserved 0014h reserved 0016h adc 0018h port a pin 7, selectable rising or falling input edge 001ah port a pin 6, selectable rising or falling input edge or comparator output 001ch port a pin 5, selectable rising or falling input edge 001eh port a pin 4, selectable rising or falling input edge 0020h port a pin 3 or port d pin 3, se lectable rising or falling input edge 0022h port a pin 2 or port d pin 2, se lectable rising or falling input edge 0024h port a pin 1, selectable rising or falling input edge 0026h port a pin 0, selectable rising or falling input edge 0028h reserved 002ah reserved 002ch reserved 002eh reserved 0030h port c pin 3, both input edges 0032h port c pin 2, both input edges 0034h port c pin 1, both input edges 0036h port c pin 0, both input edges lowest 0038h reserved
ps024315-1011 p r e l i m i n a r y architecture z8 encore! xp ? f0823 series product specification 56 architecture figure 8 displays the interrupt controller block diagram. operation this section describes th e operational aspects of the following functions. master interrupt enable : see page 56 interrupt vectors and priority : see page 57 interrupt assertion : see page 57 software interrupt assertion : see page 58 watchdog timer interrupt assertion : see page 58 master interrupt enable the master interrupt enable bit ( irqe ) in the interrupt control register globally enables and disables interrupts. interrupts are globally enabled by any of the following actions: ? execution of an enable interrupt (ei) instruction figure 8. interrupt controller block diagram vector irq request high priority medium priority low priority priority mux interrupt request latches and control port interrupts internal interrupts
ps024315-1011 p r e l i m i n a r y operation z8 encore! xp ? f0823 series product specification 57 ? execution of an return from interrupt ( iret ) instruction ? writing a 1 to the irqe bit in the interrupt control register ? interrupts are globally disabled by any of the following actions: ? execution of a disable interrupt (di ) instruction ? ez8 cpu acknowledgement of an interrupt service request from the interrupt controller ? writing a 0 to the irqe bit in the interrupt control register ? reset ? execution of a trap instruction ? illegal instruction trap ? primary oscillator fail trap ? watchdog timer oscillator fail trap interrupt vectors and priority the interrupt controller supports three levels of interrupt pr iority. level 3 is the highest priority, level 2 is the second highest prior ity, and level 1 is the lowest priority. if all interrupts are enabled with identical interrupt priority (for example, all as level 2 inter- rupts), the interrupt priority is assigned from highest to lowest as specified in table 35 on page 55. level 3 interrupts are always assign ed higher priority than level 2 interrupts which, in turn, always are assigned higher pr iority than level 1 interrupts. within each interrupt priority level (level 1, level 2 or level 3), priority is assigned as specified in table 35. reset, watchdog timer interrupt (if enabled), primary oscillator fail trap, watchdog timer oscillator fail trap, and illegal instructio n trap always have highest (level 3) priority. interrupt assertion interrupt sources assert their interrupt requests for only a single system clock period (sin- gle pulse). when the interrupt request is ac knowledged by the ez8 cpu, the correspond- ing bit in the interrupt request register is cl eared until the next interrupt occurs. writing a 0 to the corresponding bit in the interrupt re quest register likewise clears the interrupt request. zilog recommends not using a coding style that clears bits in the interrupt request reg- isters. all incoming interrupt s received between execution of the first ldx command and the final ldx comm and are lost. see example 1, which follows. caution:
ps024315-1011 p r e l i m i n a r y operation z8 encore! xp ? f0823 series product specification 58 example 1. a poor coding style that can re sult in lost interrupt requests: ldx r0, irq0 ? and r0, mask ? ldx irq0, r0 ? to avoid missing interrupts, use the coding styl e in example 2 to clear bits in the interrupt request 0 register: example 2. a good coding style that av oids lost interrupt requests: andx irq0, mask software interrupt assertion program code generates interrupts directly. writing a 1 to the correct bit in the interrupt request register triggers an interrupt (assumi ng that interrupt is enabled). when the inter- rupt request is acknowledged by the ez8 cpu, the bit in the interrupt request register is automatically cleared to 0. zilog recommends not using a coding style to generate software interrupts by setting bits in the interrupt request registers. all inco ming interrupts received between execution of the first ldx command and the final ldx co mmand are lost. see example 3, which fol- lows. example 3. a poor coding style that can re sult in lost interrupt requests: ldx r0, irq0 ? or r0, mask ? ldx irq0, r0 to avoid missing interrupts, use the coding styl e in example 4 to set bits in the interrupt request registers: example 4. a good coding style that av oids lost interrupt requests: orx irq0, mask watchdog timer interrupt assertion the watchdog timer interrupt behavior is different from interrupts generated by other sources. the watchdog timer continues to ass ert an interrupt as long as the timeout condi- tion continues. as it operates on a different (and usually slower) clock domain than the rest of the device, the watchdog timer contin ues to assert this interrupt for many system clocks until the counter rolls over. caution:
ps024315-1011 p r e l i m i n a r y interrupt control register definitions z8 encore! xp ? f0823 series product specification 59 to avoid retriggerings of the watchdog time r interrupt after exiting the associated inter- rupt service routine, zilog r ecommends that the service ro utine continues to read from the rststat register until the wdt bit is cl eared as shown in the following example. clearwdt: ? ldx r0, rststat ; read reset status register to clear wdt bit ? btjnz 5, r0, clearwdt ; loop until bit is cleared interrupt control register definitions for all interrupts other than the watchdog timer interrupt, the primary oscillator fail trap, and the watchdog timer oscillator fail trap, the interru pt control registers enable individual interrupts, set interrupt priorities, and indicate interrupt requests. interrupt requ est 0 register the interrupt request 0 (irq0) register (table 36) stores the interrupt requests for both vectored and polled interrupts. when a request is presented to the in terrupt controller, the corresponding bit in the irq0 register becom es 1. if interrupts are globally enabled (vec- tored interrupts), the interrupt controller passe s an interrupt request to the ez8 cpu. if interrupts are globally disabl ed (polled interrupts), the ez8 cpu reads the interrupt request 0 register to determine if any interrupt requests are pending. table 36. interrupt request 0 register (irq0) bit 7 6 5 4 3 2 1 0 field reserved t1i t0i u0rxi u0txi reserved adci reset 00000 0 0 r/w r/w r/w r/w r/w r/w r/w r/w address fc0h bit description [7] reserved this bit is reserved and must be programmed to 0. [6] ? t1i timer 1 interrupt request 0 = no interrupt request is pending for timer 1. 1 = an interrupt request from timer 1 is awaiting service. [5] ? t0i timer 0 interrupt request 0 = no interrupt request is pending for timer 0. 1 = an interrupt request from timer 0 is awaiting service. caution:
ps024315-1011 p r e l i m i n a r y interrupt control register definitions z8 encore! xp ? f0823 series product specification 60 interrupt requ est 1 register the interrupt request 1 (irq1) re gister (table 37) stores inte rrupt requests for both vec- tored and polled interrupts. when a request is presented to the interrupt controller, the cor- responding bit in the irq1 register beco mes 1. if interrupts are globally enabled (vectored interrupts), the interrupt controller pa sses an interrupt request to the ez8 cpu. if interrupts are globally disabl ed (polled interrupts), the ez8 cpu reads the interrupt request 1 register to determine if any interrupt requests are pending. [4] ? u0rxi uart 0 receiver interrupt request 0 = no interrupt request is pending for the uart 0 receiver. 1 = an interrupt request from the ua rt 0 receiver is awaiting service. [3] ? u0txi uart 0 transmitter interrupt request 0 = no interrupt request is pending for the uart 0 transmitter. 1 = an interrupt request from the uart 0 transmitter is awaiting service. [2:1] reserved these bits are reserved and must be programmed to 00. [0] ? adci adc interrupt request 0 = no interrupt request is pending for the adc. 1 = an interrupt request from the adc is awaiting service. table 37. interrupt request 1 register (irq1) bit 7 6 5 4 3 2 1 0 field pa7vi pa6ci pa5i pa4i pa3i pa2i pa1i pa0i reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address fc3h bit description [7] ? pa7vi port a7 interrupt request 0 = no interrupt request is pending for gpio port a. 1 = an interrupt request from gpio port a. [6] ? pa6ci port a6 or comparator interrupt request 0 = no interrupt request is pending for gpio port a or comparator. 1 = an interrupt request from gpio port a or comparator. [5:0] ? paxi port a pin x interrupt request 0 = no interrupt request is pending for gpio port a pin x. 1 = an interrupt request from gpio port a pin x is awaiting service. note: x indicates the specific gpio port pin number (0?5). bit description (continued)
ps024315-1011 p r e l i m i n a r y interrupt control register definitions z8 encore! xp ? f0823 series product specification 61 interrupt requ est 2 register the interrupt request 2 (irq2) re gister (table 38) stores inte rrupt requests for both vec- tored and polled interrupts. when a request is presented to the interrupt controller, the cor- responding bit in the irq2 register beco mes 1. if interrupts are globally enabled (vectored interrupts), the interrupt controller pa sses an interrupt request to the ez8 cpu. if interrupts are globally disabl ed (polled interrupts), the ez8 cpu can read the interrupt request 2 register to determine if any interrupt requests are pending. irq0 enable high and low bit registers table 39 describes the priority control for irq0. the irq0 enable high and low bit reg- isters (table 40 and table 41) form a prior ity-encoded enabling for interrupts in the inter- rupt request 0 register. priority is gene rated by setting bits in each register. table 38. interrupt request 2 register (irq2) bit 7 6 5 4 3 2 1 0 field reserved pc3i pc2i pc1i pc0i reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address fc6h bit description [7:4] reserved these bits are reserved and must be programmed to 0000. [3:0] ? pcxi port c pin x interrupt request 0 = no interrupt request is pending for gpio port c pin x . 1 = an interrupt request from gpio port c pin x is awaiting service. note: x indicates the specific gpio port c pin number (3?0). table 39. irq0 enable and priority encoding irq0enh[ x ] irq0enl[ x ] priority description 0 0 disabled disabled 0 1 level 1 low 1 0 level 2 nominal 1 1 level 3 high note: where x indicates the register bits from 0?7.
ps024315-1011 p r e l i m i n a r y interrupt control register definitions z8 encore! xp ? f0823 series product specification 62 table 40. irq0 enable hi gh bit register (irq0enh) bit 7 6 5 4 3 2 1 0 field reserved t1enh t0enh u0renh u0tenh reserved adcenh reset 00000 0 0 r/w r/w r/w r/w r/w r/w r/w r/w address fc1h bit description [7] reserved this bit is reserved and must be programmed to 0. [6] ? t1enh timer 1 interrupt reque st enable high bit [5] ? t0enh timer 0 interrupt reque st enable high bit [4] ? u0renh uart 0 receive interrupt request enable high bit [3] ? u0tenh uart 0 transmit interrupt request enable high bit [2:1] reserved these bits are reserved and must be programmed to 00. [0] ? adcenh adc interrupt request enable high bit table 41. irq0 enable low bit register (irq0enl) bit 7 6 5 4 3 2 1 0 field reserved t1enl t0enl u0renl u0tenl reserved adcenl reset 00000 0 0 r/w r r/w r/w r/w r/w r r/w address fc2h bit description [7] reserved this bit is reserved and must be programmed to 0 when read. [6] ? t1enl timer 1 interrupt request enable low bit
ps024315-1011 p r e l i m i n a r y interrupt control register definitions z8 encore! xp ? f0823 series product specification 63 irq1 enable high and low bit registers table 42 describes the priority control for irq1. the irq1 enable high and low bit reg- isters (table 43 and table 44) form a prior ity-encoded enabling for interrupts in the inter- rupt request 1 register. priority is gene rated by setting bits in each register. [5] ? t0enl timer 0 interrupt request enable low bit [4] ? u0renl uart 0 receive interrupt request enable low bit [3] ? u0tenl uart 0 transmit interrupt request enable low bit [2:1] reserved these bits are reserved and must be programmed to 00. [0] ? adcenl adc interrupt request enable low bit table 42. irq1 enable and priority encoding irq1enh[ x ]irq1enl[ x ] priority description 0 0 disabled disabled 0 1 level 1 low 1 0 level 2 nominal 1 1 level 3 high note: x indicates register bits 0?7. bit description (continued)
ps024315-1011 p r e l i m i n a r y interrupt control register definitions z8 encore! xp ? f0823 series product specification 64 table 43. irq1 enable hi gh bit register (irq1enh) bit 7 6 5 4 3 2 1 0 field pa7venh pa6cenh pa5enh pa4enh pa3enh pa2enh pa1enh pa0enh reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address fc4h bit description [7] ? pa7venh port a bit[7] interrupt request enable high bit [6] ? pa6cenh port a bit[7] or comparator interrupt request enable high bit [5:0] ? paxenh port a bit[ x ] interrupt request enable high bit for selection of port a as the interrupt source, see the shared interrupt select register sec- tion on page 67. note: x indicates the specific gpio port a pin number (5?0). table 44. irq1 enable low bit register (irq1enl) bit 7 6 5 4 3 2 1 0 field pa7venl pa6cenl pa5enl pa4enl pa3enl pa2enl pa1enl pa0enl reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address fc5h bit description [7] ? pa7venl port a bit[7] interrupt request enable low bit [6] ? pa6cenl port a bit[7] or comparator interrupt request enable low bit [5:0] ? paxenl port a bit[ x ] interrupt request enable low bit note: x indicates the specific gpio port a pin number (5?0).
ps024315-1011 p r e l i m i n a r y interrupt control register definitions z8 encore! xp ? f0823 series product specification 65 irq2 enable high and low bit registers table 45 describes the priority control for irq2. the irq2 enable high and low bit reg- isters (table 46 and table 47) form a prior ity encoded enabling for interrupts in the inter- rupt request 2 register. priority is gene rated by setting bits in each register. table 45. irq2 enable and priority encoding irq2enh[ x ]irq2enl[ x ] priority description 0 0 disabled disabled 0 1 level 1 low 1 0 level 2 nominal 1 1 level 3 high note: where x indicates the register bits from 0?7. table 46. irq2 enable hi gh bit register (irq2enh) bit 7 6 5 4 3 2 1 0 field reserved c3enh c2enh c1enh c0enh reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address fc7h bit description [7:4] reserved these bits are reserved and must be programmed to 0000. [3] ? c3enh port c3 interrupt requ est enable high bit [2] ? c2enh port c2 interrupt requ est enable high bit [1] ? c1enh port c1 interrupt requ est enable high bit [0] ? c0enh port c0 interrupt requ est enable high bit
ps024315-1011 p r e l i m i n a r y interrupt control register definitions z8 encore! xp ? f0823 series product specification 66 interrupt edge select register the interrupt edge select (irqes) register (table 48) determines wh ether an interrupt is generated for the rising edge or falling edge on the selected gpio port a or port d input pin. table 47. irq2 enable low bit register (irq2enl) bit 7 6 5 4 3 2 1 0 field reserved c3enl c2enl c1enl c0enl reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address fc8h bit description [7:4] reserved these bits are reserved and must be programmed to 0000. [3] ? c3enl port c3 interrupt request enable low bit [2] ? c2enl port c2 interrupt request enable low bit [1] ? c1enl port c1 interrupt request enable low bit [0] ? c0enl port c0 interrupt re quest enable high low table 48. interrupt edge select register (irqes) bit 7 6 5 4 3 2 1 0 field ies7 ies6 ies5 ies4 ies3 ies2 ies1 ies0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address fcdh bit description [7] ? iesx interrupt edge select x 0 = an interrupt request is generated on the falling edge of the pa x input or pdx. 1 = an interrupt request is generated on the rising edge of the pa x input pdx. note: x indicates the specific gpio port pin number (7?0).
ps024315-1011 p r e l i m i n a r y interrupt control register definitions z8 encore! xp ? f0823 series product specification 67 shared interrupt select register the shared interrupt select (irqss) register (table 49) determines the source of the padxs interrupts. the shared interrupt sele ct register selects between port a and ? alternate sources for the individual interrupts. because these shared interrupts are edge-trigger ed, it is possible to generate an interrupt just by switching from one shared source to another. for this reason, an interrupt must be disabled before switching between sources. table 49. shared interrupt select register (irqss) bit 7 6 5 4 3 2 1 0 field reserved pa6cs reserved reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address fceh bit description [7] reserved this bit is reserved and must be programmed to 0. [6] ? pa6cs pa6/comparator selection 0 = pa6 is used for the interrupt for pa6cs interrupt request. 1 = the comparator is used as an interrupt for pa6cs interrupt requests. [5:0] reserved these bits are reserved and must be programmed to 000000.
ps024315-1011 p r e l i m i n a r y interrupt control register definitions z8 encore! xp ? f0823 series product specification 68 interrupt control register the interrupt control (irqctl) register (table 50) contains the master enable bit for all interrupts. table 50. interrupt control register (irqctl) bit 7 6 5 4 3 2 1 0 field irqe reserved reset 00000000 r/w r/wrrrrrrr address fcfh bit description [7] ? irqe interrupt request enable this bit is set to 1 by executing an enable interr upts (ei) or interrupt re turn (iret) instruction, or by a direct register write of a 1 to this bit. it is reset to 0 by executing a di instruction, ez8 cpu acknowledgement of an interrupt request, reset or by a direct register write of a 0 to this bit. 0 = interrupts are disabled. 1 = interrupts are enabled. [6:0] reserved these bits are reserved and must be programmed to 0000000 when read.
ps024315-1011 p r e l i m i n a r y timers z8 encore! xp ? f0823 series product specification 69 timers z8 encore! xp f0823 series products contain up to two 16-bit reloadable timers that are used for timing, event counting or generatio n of pwm signals. the timers? features include: ? 16-bit reload counter ? programmable prescaler with prescale values from 1 to 128 ? pwm output generation ? capture and compare capability ? external input pin for timer input, clock gating, or capture signal; external input pin sig- nal frequency is limited to a maximum of one-fourth the system clock frequency ? timer output pin ? timer interrupt ? in addition to the timers described in this ch apter, the baud rate ge nerator of the uart (if unused) also provides basic timing functio nality. for information about using the baud rate generator as an additional timer, see the universal asynchronous receiver/transmit- ter chapter on page 97.
ps024315-1011 p r e l i m i n a r y architecture z8 encore! xp ? f0823 series product specification 70 architecture figure 9 displays the architecture of the timers. operation the timers are 16-bit up-counters. minimum tim e-out delay is set by loading the value 0001h into the timer reload high and low by te registers and setting the prescale value to 1. maximum time-out delay is set by loading the value 0000h into the timer reload high and low byte registers and setting the prescale value to 128. if the timer reaches ffffh , the timer rolls over to 0000h and continues counting. timer operating modes the timers can be configured to operate in the following modes: one-shot mode in one-shot mode, the timer co unts up to the 16-bit reload value stored in the timer reload high and low byte registers. the timer input is the system clock. upon reaching the reload value, the timer ge nerates an interrupt and the co unt value in the timer high and low byte registers is reset to 0001h . the timer is automatically disabled and stops counting. figure 9. timer block diagram 16-bit pwm/compare 16-bit counter with prescaler 16-bit reload register timer control compare compare interrupt, pwm, and timer output control timer timer block system timer data block output control bus clock input gate input capture input timer interrupt timer output complement timer output complement
ps024315-1011 p r e l i m i n a r y operation z8 encore! xp ? f0823 series product specification 71 also, if the timer output alternate function is enabled, the timer output pin changes state for one system clock cycle (fro m low to high or from high to low) upon timer reload. if it is appropriate to have the timer output ma ke a state change at a one-shot time-out (rather than a single cycle pulse), first set th e tpol bit in the timer control register to the start value before enabling one-shot mode. after starting the timer, set tpol to the opposite bit value. observe the following steps to configure a timer for one-shot mode and initiating the count: 1. write to the timer control register to: ? disable the timer ? configure the timer for one-shot mode ? set the prescale value ? set the initial output level (high or low) if using the timer ou tput alternate func- tion ? 2. write to the timer high and low byte registers to set the starting count value. 3. write to the timer reload high and low byte registers to set the reload value. 4. if appropriate, enable the timer interrupt an d set the timer interrupt priority by writing to the relevant interrupt registers. 5. if using the timer output function, configure the associated gpio port pin for the timer output alternate function. 6. write to the timer control register to enable the timer and initiate counting. ? in one-shot mode, the system clock always pr ovides the timer inpu t. the timer period is computed via th e following equation: continuous mode in continuous mode, the timer counts up to the 16-bit reload value stored in the timer reload high and low byte registers. the timer input is th e system clock. upon reaching the reload value, th e timer generates an interrupt, the count value in the timer high and low byte registers is reset to 0001h and counting resumes. also, if the timer output alternate func tion is enabled, the timer output pin changes state (from low to high or from high to low) at timer reload. observe the following steps to configure a timer for continuous mo de and to initiate the count: one-shot mode time-out period (s) reload value s tart value ? ?? prescale ? system clock frequency (hz) ----------------------------------------------------------------------------------------------- =
ps024315-1011 p r e l i m i n a r y operation z8 encore! xp ? f0823 series product specification 72 1. write to the timer control register to: ? disable the timer ? configure the timer for continuous mode ? set the prescale value ? if using the timer output alternate function, set the initial output level (high or low) 2. write to the timer high and low byte regist ers to set the starting count value (usually 0001h ). this action only affects the first p ass in continuous mode. after the first timer reload in continuous mode, countin g always begins at the reset value of 0001h . 3. write to the timer reload high and low byte registers to set the reload value. 4. enable the timer interrupt (if appropriate) an d set the timer interrupt priority by writ- ing to the relevant interrupt registers. 5. configure the associated gpio port pin (i f using the timer output function) for the timer output alternate function. 6. write to the timer control register to enable the timer and initiate counting. in continuous mode, the system clock alwa ys provides the timer input. the timer period is computed via the following equation: if an initial starting value other than 0001h is loaded into the timer high and low byte registers, use the one-shot mode equatio n to determine the first time-out period. counter mode in counter mode, the timer counts input tr ansitions from a gpio port pin. the timer input is taken from the gpio port pi n timer input alternate function. the tpol bit in the timer control register selects whether the coun t occurs on the rising edge or the falling edge of the timer input signal. in counter mode, the prescaler is disabled. the input frequency of the timer input sign al must not exceed one-fourth the system clock frequency. upon reaching the reload value stored in the timer reload high and low byte registers, the timer generates an interrupt, the count value in the ti mer high and low byte registers is reset to 0001h and counting resumes. also, if the timer output alternate function is continuous mode time-out period (s) reload value prescale ? system clock frequency (hz) ------------------------------------------------------------------------ = caution:
ps024315-1011 p r e l i m i n a r y operation z8 encore! xp ? f0823 series product specification 73 enabled, the timer output pin changes state (from low to high or from high to low) at timer reload. observe the following steps to configure a timer for counter mode and initiating the count: 1. write to the timer control register to: ? disable the timer. ? configure the timer for counter mode. ? select either the rising edge or falling edge of the timer input signal for the count. this selection also sets the initial logic level (high or low) for the timer output alternate function. ho wever, the timer output func tion is not required to be enabled. ? 2. write to the timer high and low byte regi sters to set the startin g count value. this only affects the first pass in counter mode. after the first timer reload in coun- ter mode, counting always begins at the reset value of 0001h . in counter mode the timer high and low byte register s must be written with the value 0001h . 3. write to the timer reload high and low byte registers to set the reload value. 4. if appropriate, enable the timer interrupt an d set the timer interrupt priority by writing to the relevant interrupt registers. 5. configure the associated gpio port pi n for the timer input alternate function. 6. if using the timer output function, configure the associated gpio port pin for the timer output alternate function. 7. write to the timer control re gister to enable the timer. ? in counter mode, the number of timer inpu t transitions since the timer start is com- puted via the following equation: comparator counter mode in comparator counter mode, the timer co unts input transitions from the analog comparator output. the tpol bit in the timer control regi ster selects whether the count occurs on the rising edge or the falling edge of the comparator output signal. in compar- ator counter mode, the prescaler is disabled. counter mode timer input transitions current count value start value ? =
ps024315-1011 p r e l i m i n a r y operation z8 encore! xp ? f0823 series product specification 74 the frequency of the comparator output sign al must not exceed on e-fourth the system clock frequency. after reaching the reload valu e stored in the timer reload high and low byte registers, the timer generates an interrupt, the count value in the ti mer high and low byte registers is reset to 0001h and counting resumes. also, if the timer output alternate function is enabled, the timer output pin changes state (from low to high or from high to low) at timer reload. observe the following steps to configure a timer for comparator counter mode and initiating the count: 1. write to the timer control register to: ? disable the timer. ? configure the timer for co mparator counter mode. ? select either the rising edge or falling edge of the comparator output signal for the count. this also sets the initial logic le vel (high or low) for the timer output alternate function. ho wever, the timer output func tion is not required to be enabled. 2. write to the timer high and low byte regi sters to set the startin g count value. this action only affects the first pass in co mparator counter mode. after the first timer reload in comparator counter mode, counting always begins at the reset value of 0001h . generally, in comparator counter mode the timer high and low byte registers mu st be written with the value 0001h . 3. write to the timer reload high and low byte registers to set the reload value. 4. if appropriate, enable the timer interrupt an d set the timer interrupt priority by writing to the relevant interrupt registers. 5. if using the timer output function, configure the associated gpio port pin for the timer output alternate function. 6. write to the timer control re gister to enable the timer. in comparator counter mode, the number of comparator output transitions since the timer start is computed via the following equation: caution: comparator output transitions current count value start value ? =
ps024315-1011 p r e l i m i n a r y operation z8 encore! xp ? f0823 series product specification 75 pwm single output mode in pwm single output mode, the timer outputs a pwm output signal through a gpio port pin. the timer input is the system clock. the timer first counts up to the 16-bit pwm match value stored in the timer pwm high and low byte registers. when the timer count value matches the pwm value, th e timer output toggles. the timer continues counting until it reaches the re load value stored in the timer reload high and low byte registers. upon reaching the reload value, th e timer generates an interrupt, the count value in the timer high and low byte registers is reset to 0001h and counting resumes. if the tpol bit in the timer control register is set to 1, the timer output signal begins as a high (1) and transitions to a low (0) when the timer value match es the pwm value. the timer output signal returns to a high (1) after the timer reaches the reload value and is reset to 0001h . if the tpol bit in the timer control register is set to 0, the timer output signal begins as a low (0) and transitions to a high (1) when the timer value match es the pwm value. the timer output signal returns to a low (0) after the timer reaches the reload value and is reset to 0001h . observe the following steps to configure a tim er for pwm single output mode and initiat- ing the pwm operation: 1. write to the timer control register to: ? disable the timer ? configure the timer for pwm mode ? set the prescale value ? set the initial logic level (high or low) and pwm high/low transition for the timer output alternate function ? 2. write to the timer high and low byte regi sters to set the starting count value (typi- cally 0001h ); this write only affects the first pass in pwm mode. after the first timer reset in pwm mode, counting always begins at the reset value of 0001h . 3. write to the pwm high and low byte registers to set the pwm value. 4. write to the timer reload high and low byte registers to set the reload value (pwm period). the reload value must be greater than the pwm value. 5. if appropriate, enable the timer interrupt an d set the timer interrupt priority by writing to the relevant interrupt registers. 6. configure the associated gpio port pin for the timer output alternate function. 7. write to the timer control register to enable the timer and initiate counting. the pwm period is represented by the following equation:
ps024315-1011 p r e l i m i n a r y operation z8 encore! xp ? f0823 series product specification 76 if an initial starting value other than 0001h is loaded into the timer high and low byte registers, use the one-shot mode equation to determine the first pwm time-out period. if tpol is set to 0, the ratio of the pwm output high time to the total period is represented by the following equation: if tpol is set to 1, the ratio of the pwm output high time to the total period is represented by the following equation: pwm dual output mode in pwm dual output mode, the timer outp uts a pwm output signal pair (basic pwm signal and its complement) through two gpio port pins. the timer input is the sys- tem clock. the timer first counts up to th e 16-bit pwm match value stored in the timer pwm high and low byte registers. when the timer count value matches the pwm value, the timer output toggles. the timer continu es counting until it reaches the reload value stored in the timer reload high and low byte registers. upon reaching the reload value, the timer generates an interrupt, the count value in the ti mer high and low byte registers is reset to 0001h and counting resumes. if the tpol bit in the timer control register is set to 1, the timer output signal begins as a high (1) and transitions to a low (0) when the timer value match es the pwm value. the timer output signal returns to a high (1) after the timer reaches the reload value and is reset to 0001h . if the tpol bit in the timer control register is set to 0, the timer output signal begins as a low (0) and transitions to a high (1) when the timer value match es the pwm value. the timer output signal returns to a low (0) after the timer reaches the reload value and is reset to 0001h . the timer also generates a second pwm outp ut signal timer output complement. the timer output complement is the complement of the timer output pwm signal. a pro- grammable deadband delay can be configured to time delay (0 to 128 system clock cycles) pwm output transitions on these two pins from a low to a high (inactive to active). this ensures a time gap between the deassertion of one pwm output to the assertion of its com- plement. pwm period (s) reload value prescale ? system clock frequency (hz) ------------------------------------------------------------------------ = pwm output high time ratio (%) reload value pwm value ? reload value ------------------------------------------------------------------- 100 ? = pwm output high time ratio (%) pwm value reload value ----------------------------------- - 100 ? =
ps024315-1011 p r e l i m i n a r y operation z8 encore! xp ? f0823 series product specification 77 observe the following steps to configur e a timer for pwm dual output mode and initiating the pwm operation: 1. write to the timer control register to: ? disable the timer ? configure the timer for pwm dual output mode. setting the mode also involves writing to the tmodehi bit in the txctl1 register ? set the prescale value ? set the initial logic level (high or low) and pwm high/low transition for the timer output alternate function ? 2. write to the timer high and low byte regi sters to set the starting count value (typi- cally 0001h ); this write only affects the first pass in pwm mode. after the first timer reset in pwm mode, counting always begins at the reset value of 0001h . 3. write to the pwm high and low byte registers to set the pwm value. 4. write to the pwm control register to set the pwm dead band delay value. the dead- band delay must be less than the duration of the positive phase of the pwm signal (as defined by the pwm high and low byte registers). it must also be less than the dura- tion of the negative phase of the pwm sign al (as defined by the difference between the pwm registers and the timer reload registers). 5. write to the timer reload high and low byte registers to set the reload value (pwm period). the reload value must be greater than the pwm value. 6. if appropriate, enable the timer interrupt an d set the timer interrupt priority by writing to the relevant interrupt registers. 7. configure the associated gpio port pin fo r the timer output and timer output com- plement alternate functions. the timer outp ut complement functio n is shared with the timer input function for both timers. setting the timer mode to dual pwm auto- matically switches the function from timer in to timer out complement. 8. write to the timer control register to enable the timer and initiate counting. the pwm period is represented by the following equation: if an initial starting value other than 0001h is loaded into the timer high and low byte registers, the one-shot mode equation determines the first pwm time-out period. if tpol is set to 0, the ratio of the pwm output high time to the total period is represented by: pwm period (s) reload value prescale ? system clock frequency (hz) ------------------------------------------------------------------------ =
ps024315-1011 p r e l i m i n a r y operation z8 encore! xp ? f0823 series product specification 78 if tpol is set to 1, the ratio of the pwm output high time to the total period is represented by: capture mode in capture mode, the current timer count valu e is recorded when the appropriate exter- nal timer input transition occu rs. the capture count value is written to the timer pwm high and low byte registers. the timer input is the system clock. the tpol bit in the timer control register determines if the capture occurs on a rising edge or a falling edge of the timer input signal. when the capture event occurs, an interrupt is generated and the timer continues counting. the inpcap bit in txctl1 register is set to indicate the timer interrupt is because of an input capture event. the timer continues coun ting up to the 16-bit reload valu e stored in the timer reload high and low byte registers. upon reaching th e reload value, the timer generates an inter- rupt and continues counting. the inpcap b it in txctl1 register clears indicating the timer interrupt is not becaus e of an input capture event. observe the following steps to configure a timer for capture m ode and initiating the count: 1. write to the timer control register to: ? disable the timer ? configure the timer for capture mode ? set the prescale value ? set the capture edge (rising or falling) for the timer input ? 2. write to the timer high and low byte regi sters to set the starting count value (typi- cally 0001h ). 3. write to the timer reload high and low byte registers to set the reload value. 4. clear the timer pwm high and low byte registers to 0000h . clearing these registers allows the software to determine if interrupt s were generated by either a capture or a reload event. if the pwm high and low byte registers still contain 0000h after the interrupt, the interrupt wa s generated by a reload. 5. enable the timer interrupt, if appropriate, and set the timer interr upt priority by writing to the relevant interrupt regist ers. by default, the timer in terrupt is generated for both pwm output high time ratio (%) reload value pwm value ? reload value ------------------------------------------------------------------ - 100 ? = pwm output high time ratio (%) pwm value reload value ----------------------------------- - 100 ? =
ps024315-1011 p r e l i m i n a r y operation z8 encore! xp ? f0823 series product specification 79 input capture and reload events . if appropriate, configure th e timer interrupt to be gen- erated only at the input capture event or the reload event by setting ticonfig field of the txctl1 register. 6. configure the associated gpio port pi n for the timer input alternate function. 7. write to the timer control register to enable the timer and initiate counting. in capture mode, the elapsed time from timer start to capture event can be calculated using the following equation: capture restart mode in capture restart mode, the current tim er count value is recorded when the acceptable external timer input transition occurs. the capture count value is written to the timer pwm high and low byte registers. th e timer input is the system clock. the tpol bit in the timer control register determines if the capture occurs on a rising edge or a fall- ing edge of the timer input signal. when the capture event occurs, an interrupt is gener- ated and the count value in the timer hi gh and low byte registers is reset to 0001h and counting resumes. the inpcap bit in txctl1 register is set to indicate the timer inter- rupt is because of an input capture event. if no capture event occurs, the timer counts up to the 16-bit compare value stored in the timer reload high and low byte registers. up on reaching the reload value, the timer generates an interrupt, the count value in the timer high and low byte registers is reset to 0001h and counting resumes. the inpcap bit in txctl1 register is cleared to indicate the timer interrupt is not cause d by an input capture event. observe the following steps to configure a timer for capture restart mode and ini- tiating the count: 1. write to the timer control register to: ? disable the timer ? configure the timer for capture r estart mode; setting the mode also involves writing to tmodehi bit in txctl1 register ? set the prescale value ? set the capture edge (rising or falling) for the timer input ? 2. write to the timer high and low byte regi sters to set the starting count value (typi- cally 0001h ). 3. write to the timer reload high and low byte registers to set the reload value. capture elapsed time (s) capture value start value ? ?? prescale ? system clock frequency (hz) ------------------------------------------------------------------------------------------------- - =
ps024315-1011 p r e l i m i n a r y operation z8 encore! xp ? f0823 series product specification 80 4. clear the timer pwm high and low byte registers to 0000h . clearing these registers allows the software to determine if interrupt s were generated by either a capture or a reload event. if the pwm high and low byte registers still contain 0000h after the interrupt, the interrupt wa s generated by a reload. 5. enable the timer interrupt, if appropriate, and set the timer interr upt priority by writing to the relevant interrupt regist ers. by default, the timer in terrupt is generated for both input capture and reload events . if appropriate, configure th e timer interrupt to be gen- erated only at the input capture event or the reload event by setting ticonfig field of the txctl1 register. 6. configure the associated gpio port pi n for the timer input alternate function. 7. write to the timer control register to enable the timer and initiate counting. ? in capture mode, the elapsed time from timer start to capture event can be calculated using the following equation: compare mode in compare mode, the timer counts up to the 16-bit maximum compare value stored in the timer reload high and low byte registers. the timer input is th e system clock. upon reaching the compare value, the timer genera tes an interrupt and counting continues (the timer value is not reset to 0001h ). also, if the timer output alternate function is enabled, the timer output pin changes state (from low to high or from high to low) upon com- pare. if the timer reaches ffffh , the timer rolls over to 0000h and continue counting. observe the following steps to configure a timer for compare mo de and to initiate the count: 1. write to the timer control register to: ? disable the timer ? configure the timer for compare mode ? set the prescale value ? set the initial logic level (high or low) fo r the timer output alternate function, if appropriate ? 2. write to the timer high and low byte registers to set the starting count value. 3. write to the timer reload high and low byte registers to set the compare value. 4. enable the timer interrupt, if appropriate, and set the timer interr upt priority by writing to the relevant interrupt registers. capture elapsed time (s) capture value start value ? ?? prescale ? system clock frequency (hz) ------------------------------------------------------------------------------------------------- - =
ps024315-1011 p r e l i m i n a r y operation z8 encore! xp ? f0823 series product specification 81 5. if using the timer output function, configure the associated gpio port pin for the timer output alternate function. 6. write to the timer control register to enable the timer and initiate counting. ? in compare mode, the system clock always provides the timer inpu t. the compare time can be calculated by the following equation: gated mode in gated mode, the timer counts only when the timer input si gnal is in its active state (asserted), as determined by the tpol bit in the timer control register. when the timer input signal is asserted, counting begins. a timer interrupt is generated when the timer input signal is deasserted or a timer reload occurs. to determine if a timer input signal deassertion generated the interrupt, read the as sociated gpio input value and compare to the value stored in the tpol bit. the timer counts up to the 16-bit reload value stored in th e timer reload high and low byte registers. the timer input is the system clock. when r eaching the reload value, the timer generates an interrupt, the count value in the timer high and low byte registers is reset to 0001h and counting resumes (assuming the ti mer input signal remains asserted). also, if the timer output alternate function is enabled, the timer output pin changes state (from low to high or from hi gh to low) at timer reset. observe the following steps to configure a timer for gated mode and to initiate the count: 1. write to the timer control register to: ? disable the timer ? configure the timer for gated mode ? set the prescale value 2. write to the timer high and low byte registers to set the starting count value. writing these registers only affects the first pass in gated mode. after the first timer reset in gated mode, counting always begins at the reset value of 0001h . 3. write to the timer reload high and low byte registers to set the reload value. 4. enable the timer interrupt, if appropriate, and set the timer interr upt priority by writing to the relevant interrupt regist ers. by default, the timer in terrupt is generated for both input deassertion and reload events. if appropri ate, configure the timer interrupt to be generated only at the input deassertion even t or the reload event by setting ticonfig field of the txctl1 register. compare mode time (s) compare value start value ? ?? prescale ? system clock frequency (hz) ---------------------------------------------------------------------------------------------------- - =
ps024315-1011 p r e l i m i n a r y operation z8 encore! xp ? f0823 series product specification 82 5. configure the associated gpio port pi n for the timer input alternate function. 6. write to the timer control re gister to enable the timer. 7. assert the timer input signal to initiate the counting. capture/compare mode in capture/compare mode, the timer begins counting on the first external timer input transition. the acceptable transition (risi ng edge or falling edge) is set by the tpol bit in the timer control register. th e timer input is th e system clock. every subsequent acceptable transition (after the first) of the timer input signal captures the current count value. the capture value is written to the timer pwm high and low byte registers. when the capture event occurs, an interrupt is generated, the count value in the timer high and low byte registers is reset to 0001h , and counting resumes. the inpcap bit in txctl1 register is set to indicat e the timer interrupt is caused by an input capture event. if no capture event occurs, the timer counts up to the 16-bit compare value stored in the timer reload high and low byte registers. up on reaching the compare value, the timer generates an interrupt, the count value in the timer high and low byte registers is reset to 0001h and counting resumes. the inpcap bit in txctl1 register is cleared to indicate the timer interrupt is not because of an input capture event. observe the following steps to configure a timer for capture/compare mode and initiating the count: 1. write to the timer control register to: ? disable the timer ? configure the timer for capture/compare mode ? set the prescale value ? set the capture edge (rising or falling) for the timer input ? 2. write to the timer high and low byte regi sters to set the starting count value (typi- cally 0001h ). 3. write to the timer reload high and low byte registers to set the compare value. 4. enable the timer interrupt, if appropriate, and set the timer interr upt priority by writing to the relevant interrupt registers.by defau lt, the timer interrupt are generated for both input capture and reload events . if appropriate, configure th e timer interrupt to be gen- erated only at the input capture event or the reload event by setting ticonfig field of the txctl1 register. 5. configure the associated gpio port pi n for the timer input alternate function. 6. write to the timer control re gister to enable the timer.
ps024315-1011 p r e l i m i n a r y timer control register definitions z8 encore! xp ? f0823 series product specification 83 7. counting begins on the first appropriate tr ansition of the timer input signal. no inter- rupt is generated by this first edge. ? in capture/compare mode, the elapsed time from timer start to capture event can be calculated using the following equation: reading the timer count values the current count va lue in the timers can be read while counting (enabled). this capability has no effect on timer operation. when the timer is enabled and the timer high byte reg- ister is read, the contents of the timer low byte register are placed in a holding register. a subsequent read from the timer low byte register returns the value in the holding register. this operation allows accurate reads of the full 16-bit time r count value while enabled. when the timers are not enabled, a read fro m the timer low byte register returns the actual value in the counter. timer pin signal operation timer output is a gpio port pin alternate function. the timer output is toggled every time the counter is reloaded. the timer input can be used as a selectable counting source. it shares the same pin as the complementary timer output. when selected by the gpio alternate function registers, this pin functions as a timer input in all modes except for the dual pwm output mode. for this mode, there is no timer input available. timer control register definitions this section defines the features of the following timer control registers. timer 0?1 high and low byte registers : see page 83 timer reload high and low byte registers : see page 84 timer 0?1 pwm high and low byte registers : see page 86 timer 0?1 control registers : see page 86 timer 0?1 high and low byte registers the timer 0?1 high and low byte (txh and tx l) registers (table 51 and table 52) con- tain the current 16-bit timer count value. wh en the timer is enabled, a read from txh capture elapsed time (s) capture value start value ? ?? prescale ? system clock frequency (hz) ----------------------------------------------------------------------------------------------------------------------- - =
ps024315-1011 p r e l i m i n a r y timer control register definitions z8 encore! xp ? f0823 series product specification 84 causes the value in txl to be stored in a temporary holding register. a read from txl always returns this temporary register when the timers are enabled. when the timer is dis- abled, reads from the txl reads the register directly. writing to the timer high and low byte regist ers while the timer is enabled is not recom- mended. there are no temporary holding regist ers available for write operations, so simul- taneous 16-bit writes are not possible. if eith er the timer high or low byte registers are written during counting, the 8- bit written value is placed in the counter (high or low byte) at the next clock edge. the coun ter continues counting from the new value. timer reload high and low byte registers the timer 0?1 reload high and low byte (txrh and txrl) registers (table 53 and table 54) store a 16-bit reload value, {trh[7 :0], trl[7:0]}. values written to the timer reload high byte register are stored in a te mporary holding register. when a write to the timer reload low byte register occurs, the te mporary holding register value is written to the timer high byte register. this operation allows simultaneous updates of the 16-bit timer reload value. in comp are mode, the timer reload high and low byte registers store the 16-bit compare value. table 51. timer 0?1 high byte register (txh) bit 7 6 5 4 3 2 1 0 field th reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f00h, f08h table 52. timer 0?1 low byte register (txl) bit 7 6 5 4 3 2 1 0 field tl reset 00000001 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f01h, f09h bit description [7:0] ? th, tl timer high and low bytes these 2 bytes, {th[7:0], tl[7:0]}, contain the current 16-bit timer count value.
ps024315-1011 p r e l i m i n a r y timer control register definitions z8 encore! xp ? f0823 series product specification 85 trh and trl?timer reload register high and low ? these two bytes form the 16-bit reload value, {trh[7:0], trl[7:0]}. this value sets the maximum count valu e which initiates a timer reload to 0001h . in compare mode, these two bytes form th e 16-bit compare value. table 53. timer 0?1 reload high byte register (txrh) bit 7 6 5 4 3 2 1 0 field trh reset 11111111 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f02h, f0ah table 54. timer 0?1 reload low byte register (txrl) bit 7 6 5 4 3 2 1 0 field trl reset 11111111 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f03h, f0bh bit description [7] ? [6] ? [5] ? [4] ? [3] ? [2] ? [1] ? [0] ?
ps024315-1011 p r e l i m i n a r y timer control register definitions z8 encore! xp ? f0823 series product specification 86 timer 0?1 pwm high and low byte registers the timer 0?1 pwm high and low byte (txpwmh and txpwml) registers (table 55 and table 56) control pulse-width modulator (p wm) operations. these registers also store the capture values for the captu re and capture/compare modes. timer 0?1 control registers the timer control registers are 8-bit read/write registers that control the operation of their associated counter/timers. timer 0?1 control register 0 the timer control register 0 (txctl0) and timer control register 1 (txctl1) deter- mine the timer operating mode. it also in cludes a programmable pwm deadband delay, table 55. timer 0?1 pwm high byte register (txpwmh) bit 7 6 5 4 3 2 1 0 field pwmh reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f04h, f0ch table 56. timer 0?1 pwm low byte register (txpwml) bit 7 6 5 4 3 2 1 0 field pwml reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f05h, f0dh bit description [7:0] ? pwmh, pwml pulse-width modulator high and low bytes these two bytes, {pwmh[7:0], pwml[7:0]}, form a 16 -bit value that is compared to the current 16-bit timer count. when a match occurs, t he pwm output changes state. the pwm output value is set by the tpol bit in the timer control register (txctl1) ? register. ? ? these txpwmh and txpwml registers also store the 16-bit captured timer value when oper- ating in capture or capture/comp are modes.
ps024315-1011 p r e l i m i n a r y timer control register definitions z8 encore! xp ? f0823 series product specification 87 two bits to configure timer interrupt definitio n, and a status bit to identify if the most recent timer interrupt is caused by an input capture event. timer 0?1 control register 1 the timer 0?1 control (txctl1) registers en able/disable the timers, set the prescaler value, and determine the timer operating mode. table 57. timer 0?1 control register 0 (txctl0) bit 7 6 5 4 3 2 1 0 field tmodehi ticonfig reserved pwmd inpcap reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f06h, f0eh bit description [7] ? tmodehi timer mode high bit this bit along with the tmode field in txctl1 register determines the operating mode of the timer. this is the mo st-significant bit of the timer mode selection value. [6:5] ? ticonfig timer interrupt configuration this field configures ti mer interrupt definition. 0x = timer interrupt occurs on all defined reload, compare and input events. 10 = timer interrupt only on defi ned input capture/deassertion events. 11 = timer interrupt only on defined reload/compare events. [4] reserved this bit is reserved and must be programmed to 0. [3:1] ? pwmd pwmd?pwm delay value this field is a programmable delay to cont rol the number of system clock cycles delay before the timer output and th e timer output complement are forced to their active state. 000 = no delay. ? 001 = 2 cycles delay. ? 010 = 4 cycles delay. ? 011 = 8 cycles delay. ? 100 = 16 cycles delay. ? 101 = 32 cycles delay. ? 110 = 64 cycles delay. ? 111 = 128 cycles delay. [0] ? inpcap input capture event this bit indicates if the most recent timer inte rrupt is caused by a timer input capture event. 0 = previous timer interrupt is not a result of timer input capture event. 1 = previous timer interrupt is a re sult of timer input capture event.
ps024315-1011 p r e l i m i n a r y timer control register definitions z8 encore! xp ? f0823 series product specification 88 table 58. timer 0?1 control register 1 (txctl1) bit 7 6 5 4 3 2 1 0 field ten tpol pres tmode reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f07h, f0fh bit description [7] ? ten timer enable 0 = timer is disabled. 1 = timer enabled to count. [6] ? tpol timer input/output polarity operation of this bit is a function of the current operating mode of the timer. one-shot mode when the timer is disabled, the timer output sig nal is set to the value of this bit. when the timer is enabled, the timer output signal is complemented upon timer reload. continuous mode when the timer is disabled, the timer output sig nal is set to the value of this bit. when the timer is enabled, the timer output signal is complemented upon timer reload.
ps024315-1011 p r e l i m i n a r y timer control register definitions z8 encore! xp ? f0823 series product specification 89 [6] ? tpol (cont?d.) counter mode if the timer is enabled the timer output signal is complemented after timer reload. 0 = count occurs on the rising edge of the timer input signal. 1 = count occurs on the falling ed ge of the timer input signal. pwm single output mode 0 = timer output is forced low (0) when the timer is disabled. when enabled, the timer output is forced high (1) upon pwm count match and forced low (0) upon reload. 1 = timer output is forced high (1) when the timer is disabled. when enabled, the timer out- put is forced low (0) upon pwm count match and forced high (1) upon reload. capture mode 0 = count is captured on the rising edge of the timer input signal. 1 = count is captured on the fallin g edge of the time r input signal. compare mode when the timer is disabled, the timer output sig nal is set to the value of this bit. when the timer is enabled, the timer output signal is complemented upon timer reload. gated mode 0 = timer counts when the timer input signal is high (1) and interrupts are generated on the falling edge of the timer input. 1 = timer counts when the timer input signal is low (0) and interrupts are generated on the rising edge of the timer input. capture/compare mode 0 = counting is started on the first rising edge of the timer input signal. the current count is captured on subsequent rising ed ges of the timer input signal. 1 = counting is started on the first falling edge of the timer input signal. the current count is captured on s ubsequent falling edges of the timer i nput signal. pwm dual output mode 0 = timer output is forced low (0) and timer output complement is forced high (1) when the timer is disabled. when enabled, the timer output is forced high (1) upon pwm count match and forced low (0) upon reload. when en abled, the timer output complement is forced low (0) upon pwm count match and forc ed high (1) upon reload. the pwmd field in txctl0 register is a programmable delay to control the number of cycles time delay before the timer output and the timer outp ut complement is forced to high (1). 1 = timer output is forced high (1) and timer output complement is forced low (0) when the timer is disabled. when enabled, the timer output is forced low (0) upon pwm count match and forced high (1) upon reload.when enabled, the timer output complement is forced high (1) upon pwm count match and fo rced low (0) upon reload. the pwmd field in txctl0 register is a programmable delay to control the number of cycles time delay before the timer output and the timer ou tput complement is forced to low (0). capture restart mode 0 = count is captured on the rising edge of the timer input signal. 1 = count is captured on the fallin g edge of the time r input signal. bit description (continued)
ps024315-1011 p r e l i m i n a r y timer control register definitions z8 encore! xp ? f0823 series product specification 90 [6] ? tpol (cont?d.) comparator counter mode when the timer is disabled, the timer output sig nal is set to the value of this bit. when the timer is enabled, the timer output signal is complemented upon timer reload. ? caution: when the timer output alternate function txout on a gpio port pin is enabled, txout changes to whatever state the tpol bit is in. the timer does not need to be enabled for that to happen. also, the port data direction sub register is not needed to be set to output on txout. changing the tpol bit with the timer enabled and running does not immediately change the txout. [5:3] ? pres prescale value the timer input clock is divided by 2 pres , where pres can be set from 0 to 7. the prescaler is reset each time the timer is disabled. this reset ensures proper clock division each time the timer is restarted. 000 = divide by 1. 001 = divide by 2. 010 = divide by 4. 011 = divide by 8. 100 = divide by 16. 101 = divide by 32. 110 = divide by 64. 111 = divide by 128. [2:0] ? tmode timer mode this field, along with the tmodehi bit in txct l0 register, determines the operating mode of the timer. tmodehi is the most significan t bit of the timer mode selection value. 0000 = one-shot mode. 0001 = continuous mode. 0010 = counter mode. 0011 = pwm single output mode. 0100 = capture mode. 0101 = compare mode. 0110 = gated mode. 0111 = capture/compare mode. 1000 = pwm dual output mode. 1001 = capture restart mode. 1010 = comparator counter mode. bit description (continued)
ps024315-1011 p r e l i m i n a r y watchdog timer z8 encore! xp ? f0823 series product specification 91 watchdog timer the watchdog timer (wdt) protects against co rrupt or unreliable software, power faults, and other system-level proble ms which can place z8 encore! xp f0823 series devices into unsuitable operating states. the features of watchdog timer include: ? on-chip rc oscillator ? a selectable time-out response: reset or interrupt ? 24-bit programmable time-out value operation the wdt is a retriggerable one-shot timer that resets or interrupts f0823 series devices when the wdt reaches its terminal count. th e watchdog timer uses a dedicated on-chip rc oscillator as its clock source. the watchdo g timer operates in only two modes: on and off. once enabled, it always counts and mu st be refreshed to prevent a time-out. per- form an enable by executing the wdt instruction or by settin g the wdt_ao flash option bit. the wdt_ao bit forces the watchdog timer to operate immediately upon reset, even if a wdt instruction has not been executed. the watchdog timer is a 24-bit reloadable down counter that uses three 8-bit registers in the ez8 cpu register space to set the reload value. the nominal wdt time-out period is described by the following equation: where the wdt reload value is the deci mal value of the 24-bit value given by {wdtu[7:0], wdth[7:0], wdtl[7:0]} and the typical watchdog timer rc oscillator frequency is 10 khz. the watchdog ti mer cannot be refreshed after it reaches 000002h . the wdt reload value must no t be set to values below 000004h . table 59 provides information about approxim ate time-out delays for the minimum and maximum wdt reload values. table 59. watchdog timer approximate time-out delays wdt reload value (hex) wdt reload value (decimal) approximate time-out delay (with 10 khz typical wdt oscillator frequency) typical description 000004 4 400 ? s minimum time-out delay ffffff 16,777,215 28 minutes maximum time-out delay wdt time-out period (ms) wdt reload value 10 --------------- -------------- ------------- =
ps024315-1011 p r e l i m i n a r y operation z8 encore! xp ? f0823 series product specification 92 watchdog timer refresh when first enabled, the wdt is loaded with the value in th e watchdog timer reload reg- isters. the watchdog timer counts down to 000000h unless a wdt instruction is executed by the ez8 cpu. execution of the wdt instruction causes the down counter to be reloaded with the wdt reload value stored in the watchdog timer reload registers. counting resumes following th e reload operation. when z8 encore! xp f0823 series devices are operating in debug mode (using the ocd), the watchdog timer is continuously refreshed to prevent any watchdog timer time-outs. watchdog timer time-out response the watchdog timer times ou t when the counter reaches 000000h . a time-out of the watchdog timer generates either an interru pt or a system reset. the wdt_res flash option bit determines the time-out response of the watchdog time r. for information about programming of the wdt_res flash option bit, see the flash option bits chapter on page 146. wdt interrupt in normal operation if configured to generate an interrupt when a time-out occu rs, the watchdog timer issues an interrupt request to the interrupt controller and sets the wdt status bit in the watchdog timer control register. if interrupts are enabled, the ez8 cpu responds to the interrupt request by fetching the watch dog timer interrupt vector an d executing code from the vec- tor address. after time-out and interrupt ge neration, the watchdog timer counter rolls over to its maximum value of fffffh and continues counting. the watchdog timer counter is not automatically re turned to its reload value. the reset status register (see the reset status register section on page 28) must be read before clearing the wdt interrupt. this read clears the wdt time-out flag and prevents further wdt interrupts fo r immediately occurring. wdt interrupt in stop mode if configured to generate an interrupt when a time-out occu rs and f0823 series are in stop mode, the watchdog timer automatically initiates a st op mode recovery and gen- erates an interrupt request. bo th the wdt status bit and the stop bit in the watchdog timer control register are set to 1 followi ng a wdt time-out in stop mode. for more information about stop mode recovery, see the reset and stop mode recovery chapter on page 21. if interrupts are enabled, following completi on of the stop mode recovery the ez8 cpu responds to the interrupt request by fetching the watchdog timer interrupt vector and exe- cuting code from the vector address.
ps024315-1011 p r e l i m i n a r y watchdog timer control register z8 encore! xp ? f0823 series product specification 93 wdt reset in normal operation if configured to generate a reset when a tim e-out occurs, the watchdog timer forces the device into the system reset state. the wd t status bit in the watchdog timer control register is set to 1. for more in formation about system reset, see the reset and stop mode recovery chapter on page 21. wdt reset in stop mode if configured to generate a reset when a time- out occurs and the device is in stop mode, the watchdog timer initiates a stop mode recovery. both the wdt status bit and the stop bit in the watchdog timer control register are set to 1 following wdt time-out in stop mode. for more information, see the reset and stop mode recovery chapter on page 21. watchdog timer relo ad unlock sequence writing the unlock sequence to the watchdog timer cont rol register (wdtctl) address unlocks the three watchdog timer reload byte registers (wdtu, wdth, and wdtl) to allow changes to the time- out period. these write operations to the wdtctl register address produce no effect on the bits in the wdtctl register. the locking mechanism prevents spurious writes to the reload registers. the fo llowing sequence is required to unlock the watchdog timer reload byte registers (wdtu, wdth, and wdtl) for write access. 1. write 55h to the watchdog timer control register (wdtctl). 2. write aah to the watchdog timer control register (wdtctl). 3. write the watchdog timer reload upper byte register (wdtu). 4. write the watchdog timer reload high byte register (wdth). 5. write the watchdog timer relo ad low byte register (wdtl). ? all three watchdog timer reload registers must be written in the order just listed. there must be no other register writes between each of these operations. if a register write occurs, the lock state machine resets and no further writes can occur unless the sequence is restarted. the value in the watchdog timer re load registers is loaded into the counter when the watchdog timer is first enabled and every time a wdt instruction is executed. watchdog timer control register definitions this section defines the features of the fo llowing watchdog timer control registers. watchdog timer control register (wdtctl) : see page 94 watchdog timer reload upper byte register (wdtu) : see page 95
ps024315-1011 p r e l i m i n a r y watchdog timer control register z8 encore! xp ? f0823 series product specification 94 watchdog timer reload high byte register (wdth) : see page 95 watchdog timer reload lo w byte register (wdtl) : see page 95 watchdog timer control register the watchdog timer control (wdtctl) register is a write-only control register. writing the 55h , aah unlock sequence to the wdtctl regist er address unlocks the three watch- dog timer reload byte registers (wdtu, wdth and wdtl) to allow changes to the time-out period. these write operations to the wdtctl register address produce no effect on the bits in the wdtctl register . the locking mechanism prevents spurious writes to the reload registers. this register address is shared with the read-only reset status register. watchdog timer reload upper, high and low byte registers the watchdog timer reload upper, high and low byte (wdtu, wdth, wdtl) regis- ters, shown in tables 61 through 63, form the 24-bit reload value that is loaded into the watchdog timer when a wdt instruction executes. the 24-b it reload value ranges across bits [23:0] to encompass the three bytes {wdtu[7:0], wdth[7:0], wdtl[7:0]}. writ- ing to these registers sets the appropriate reload value. reading from these registers returns the current watchdog timer count value. the 24-bit wdt reload value must no t be set to a value less than 000004h . table 60. watchdog timer control register (wdtctl) bit 7 6 5 4 3 2 1 0 field wdtunlk reset xxxxxxxx r/w wwwwwwww address ff0h bit description [7:0] ? wdtunlk watchdog timer unlock the software must write the correct unlocking se quence to this register before it is allowed to modify the contents of t he watchdog timer reload registers. caution:
ps024315-1011 p r e l i m i n a r y watchdog timer control register z8 encore! xp ? f0823 series product specification 95 table 61. watchdog timer reload upper byte register (wdtu) bit 7 6 5 4 3 2 1 0 field wdtu reset 00h r/w r/w* r/w* r/w* r/w* r/w* r/w* r/w* r/w* address ff1h note: r/w*?read returns the current wdt count val ue. write sets the appropriate reload value. bit description [7:0] ? wdtu wdt reload upper byte most significant byte (msb), bits[23:16], of the 24-bit wdt reload value. table 62. watchdog timer reload high byte register (wdth) bit 7 6 5 4 3 2 1 0 field wdth reset 04h r/w r/w* r/w* r/w* r/w* r/w* r/w* r/w* r/w* address ff2h note: r/w*?read returns the current wdt count val ue. write sets the appropriate reload value. bit description [7:0] ? wdth wdt reload high byte middle byte, bits[15:8], of the 24-bit wdt reload value. table 63. watchdog timer reload low byte register (wdtl) bit 7 6 5 4 3 2 1 0 field wdtl reset 00h r/w r/w* r/w* r/w* r/w* r/w* r/w* r/w* r/w* address ff3h note: r/w*?read returns the current wdt count val ue. write sets the appropriate reload value.
ps024315-1011 p r e l i m i n a r y watchdog timer control register z8 encore! xp ? f0823 series product specification 96 bit description [7:0] ? wdtl wdt reload low least significant byte (lsb), bits[7:0 ], of the 24-bit wdt reload value.
ps024315-1011 p r e l i m i n a r y universal asynchronous receiver/ z8 encore! xp ? f0823 series product specification 97 universal asynchronous receiver/ transmitter the universal asynchronous re ceiver/transmitter (uart) is a full-duplex communication channel capable of handling asynchronous data transfers. the uart uses a single 8-bit data mode with selectable parity. the features of uart include: ? 8-bit asynchronous data transfer ? selectable even- and odd-parity generation and checking ? option of one or two stop bits ? separate transmit and receive interrupts ? framing, parity, overrun, and break detection ? separate transmit and receive enables ? 16-bit baud rate generator (brg) ? selectable multiprocessor (9-bit) mode with three configurable interrupt schemes ? brg can be configured and used as a basic 16-bit timer ? driver enable output for external bus transceivers architecture the uart consists of three primary functional blocks: transmitter, rece iver, and baud rate generator. the uart?s transmitter and receiv er function independently, but employ the same baud rate and data format. figur e 10 displays the uart architecture.
ps024315-1011 p r e l i m i n a r y operation z8 encore! xp ? f0823 series product specification 98 operation the uart always transmits and receives data in an 8-bit data format, least-significant bit (lsb) first. an even or odd parity bit can be added to the data stream. each character begins with an active low start bit and ends with eith er 1 or 2 active high stop bits. figure 11 and figure 12 display the asynchronous data format employed by the uart without par- ity and with parity, respectively. figure 10. uart block diagram receive shifter receive data transmit data transmit shift txd rxd system bus parity checker parity generator receiver control control registers transmitter control cts status register register register register baud rate generator de with address compare
ps024315-1011 p r e l i m i n a r y operation z8 encore! xp ? f0823 series product specification 99 transmitting data us ing the polled method observe the following steps to transmit da ta using the polled method of operation: 1. write to the uart baud rate high and low byte registers to set the required baud rate. 2. enable the uart pin functions by config uring the associated gpio port pins for alternate function operation. 3. write to the uart control 1 register, if multiprocessor mode is appropriate, to enable multiprocessor (9-bit) mode functions. 4. set the multiprocessor mode select ( mpen ) bit to enable multiprocessor mode. 5. write to the uart control 0 register to: ? set the transmit enable bit ( ten ) to enable the uart for data transmission ? set the parity enable bit ( pen ), if parity is approp riate and multiprocessor mode is not enabled, and select either even or odd parity ( psel ) figure 11. uart asynchronous data format without parity figure 12. uart asynchronous data format with parity start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 data field lsb msb idle state of line stop bit(s) 1 2 1 0 start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity data field lsb msb idle state of line stop bit(s) 1 2 1 0
ps024315-1011 p r e l i m i n a r y operation z8 encore! xp ? f0823 series product specification 100 ? set or clear the ctse bit to enable or disable control from the remote receiver using the cts pin ? 6. check the tdre bit in the uart status 0 register to determine if the transmit data register is empty (indicated by a 1). if empty, continue to step 7 . if the transmit data register is full (indicated by a 0), continue to monitor the tdre bit until the transmit data register becomes ava ilable to receive new data. 7. write the uart control 1 register to select the outgoing address bit. 8. set the multiprocessor bit transmitter ( mpbt ) if sending an address byte, clear it if sending a data byte. 9. write the data byte to the uart transm it data register. the transmitter automati- cally transfers the data to the transmit shift register and transmits the data. 10. make any changes to the multiprocessor bit transmitter ( mpbt ) value, if appropriate and multiprocessor mode is enabled,. 11. to transmit additional bytes, return to step 5 . transmitting data using the interrupt-driven method the uart transmitter interrupt indicates the ava ilability of the transmit data register to accept new data for transmission. observe the following steps to configure the uart for ? interrupt-driven data transmission: 1. write to the uart baud rate high and low byte registers to set the appropriate baud rate. 2. enable the uart pin functions by config uring the associated gpio port pins for alternate function operation. 3. execute a di instruction to disable interrupts. 4. write to the interrupt control registers to enable the uart transmitter interrupt and set the acceptable priority. 5. write to the uart control 1 register to enable multiprocessor (9-bit) mode functions, if multiprocess or mode is appropriate. 6. set the multiprocessor mode select ( mpen ) to enable multiprocessor mode. 7. write to the uart control 0 register to: ? set the transmit enable bit ( ten ) to enable the uart for data transmission. ? enable parity, if appropriate and if multiprocessor mode is not enabled, and select either even or odd parity.
ps024315-1011 p r e l i m i n a r y operation z8 encore! xp ? f0823 series product specification 101 ? set or clear ctse to enable or disable control fro m the remote receiver using the cts pin. 8. execute an ei instruction to enable interrupts. the uart is now configured for interrupt-d riven data transmission. because the uart transmit data register is empty, an interru pt is generated immediately. when the uart transmit interrupt is detected, the associated interrupt service routine (isr) performs the following: 1. write the uart control 1 register to select the multiprocessor bit for the byte to be transmitted: set the multiprocessor bit transmitter ( mpbt ) if sending an address byte, clear it if sending a data byte. 2. write the data byte to the uart transm it data register. the transmitter automati- cally transfers the data to the transmit shift register and transmits the data. 3. clear the uart transmit interrupt bit in th e applicable interrupt request register. 4. execute the iret instruction to return from the interrupt-service routine and wait for the transmit data register to again become empty. receiving data using the polled method observe the following steps to config ure the uart for polled data reception: 1. write to the uart baud rate high and low byte registers to set an acceptable baud rate for the incoming data stream. 2. enable the uart pin functions by config uring the associated gpio port pins for alternate function operation. 3. write to the uart control 1 register to enable multiprocessor mode func- tions, if appropriate. 4. write to the uart control 0 register to: ? set the receive enable bit ( ren ) to enable the uart for data reception ? enable parity, if appropriate and if multiprocessor mode is not enabled, and select either even or odd parity 5. check the rda bit in the uart status 0 register to determine if the receive data register contains a valid data byte (indicated by a 1). if rda is set to 1 to indicate available data, continue to step 6 . if the receive data register is empty (indicated by a 0), continue to monito r the rda bit awaiting reception of the valid data. 6. read data from the uart receive data register. if operating in multiproces- sor (9-bit) mode, further actions may be required depending on the multipro- cessor mode bits mpmd[1:0].
ps024315-1011 p r e l i m i n a r y operation z8 encore! xp ? f0823 series product specification 102 7. return to step 4 to receive additional data. receiving data using the interrupt-driven method the uart receiver interrupt indicates the availa bility of new data (as well as error condi- tions). observe the following steps to conf igure the uart receiver for interrupt-driven operation: 1. write to the uart baud rate high and low byte registers to set the acceptable baud rate. 2. enable the uart pin functions by config uring the associated gpio port pins for alternate function operation. 3. execute a di instruction to disable interrupts. 4. write to the interrupt control registers to enable the uart receiver interrupt and set the acceptable priority. 5. clear the uart receiver interrupt in th e applicable interrupt request register. 6. write to the uart control 1 register to enable multiprocessor (9-bit) mode func- tions, if appropriate. ? set the multiprocessor mode select ( mpen ) to enable multiprocessor mode ? set the multiprocessor mode bits, mpmd[1:0] , to select the acceptable address matching scheme ? configure the uart to interrupt on received data and errors or errors only (inter- rupt on errors only is unlikel y to be useful for z8 en core! xp devices without a dma block) ? 7. write the device address to the address compare register (automatic multipro- cessor modes only). 8. write to the uart control 0 register to: ? set the receive enable bit ( ren ) to enable the uart for data reception ? enable parity, if appropriate and if multip ro cessor mode is not enabled, and select either even or odd parity ? 9. execute an ei instruction to enable interrupts. ? the uart is now configured for interrupt-driven data reception. when the uart receiver interrupt is detected, the associat ed interrupt service routine (isr) performs the following:
ps024315-1011 p r e l i m i n a r y operation z8 encore! xp ? f0823 series product specification 103 1. checks the uart status 0 register to dete rmine the source of the interrupt - error, break, or received data. 2. reads the data from the uart receive data register if the interrupt was because of data available. if operating in multipro cessor (9-bit) mode, further actions may be required depending on the mult iprocessor mode bits mpmd[1:0]. 3. clears the uart receiver interrupt in the applicable interrupt request register. 4. executes the iret instruction to return from the in terrupt-service routine and await more data. clear to send ( cts ) operation the cts pin, if enabled by the ctse bit of the uart control 0 register, performs flow control on the outgoing transmit datastream. the clear to send (cts ) input pin is sam- pled one system clock before beginning any new character transmission. to delay trans- mission of the next data character, an external receiver must deassert cts at least one system clock cycle before a new data transm ission begins. for multiple character trans- missions, this action is typically perform ed during stop bit transmission. if cts deasserts in the middle of a character transmission, the current character is sent completely. multiprocessor (9-bit) mode the uart has a multiprocessor (9-bit) mode that uses an extra (9 th ) bit for selec- tive communication when a number of proce ssors share a common uart bus. in multi- processor mode (also referred to as 9- bit mode), the mu ltiprocessor bit ( mp ) is transmitted immediately following the 8-bits of data and immediately preceding the stop bit(s) as displayed in figure 13. the character format is given below: in multiprocessor (9-bit) mode , the parity bit location (9 th bit) becomes the multi- processor control bit. the uart control 1 and status 1 registers provide multipro- cessor (9-bit) mode co ntrol and status information. if an automatic address matching figure 13. uart asynchronous multiprocessor mode data format start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 mp data field lsb msb idle state of line stop bit(s) 1 2 1 0
ps024315-1011 p r e l i m i n a r y operation z8 encore! xp ? f0823 series product specification 104 scheme is enabled, the uart ad dress compare register holds the network address of the device. multiprocessor (9-bit) mode receive interrupts when multiprocessor mode is enabled, the uart only processes frames addressed to it. the determination of whether a frame of data is addressed to the uart can be made in hardware, software or so me combination of the two, depending on the multiprocessor configuration bits. in general, the address co mpare feature reduces the load on the cpu, because it does not require access to the uart when it receives data directed to other devices on the multi-node network. the fo llowing three multip rocessor modes are available in hardware: ? interrupt on all address bytes ? interrupt on matched address bytes and correctly framed data bytes ? interrupt only on corre ctly framed data bytes ? these modes are selected with mpmd[1:0] in the uart control 1 register. for all multi- processor modes, bit mpen of the uart control 1 register must be set to 1. the first scheme is enabled by writing 01b to mpmd[1:0]. in this mode, all incoming address bytes cause an interrupt, while data bytes never cause an interrupt. the interrupt service routine must manually check the addre ss byte that caused triggered the interrupt. if it matches the uart address, the software clears mpmd[0]. each new incoming byte interrupts the cpu. the software is responsib le for determining the end of the frame. it checks for the end-o f-frame by reading the mprx bit of the uart status 1 register for each incoming byte. if mprx = 1, a new frame has begun. if the address of this new frame is different from the uart?s address, mpmd[0] must be set to 1 causing the uart inter- rupts to go inactive until the next address byte. if the new frame?s address matches the uart?s, the data in the new frame is processed as well. the second scheme requires th e following: set mpmd[1:0] to 10b and write the uart?s address into the uart address co mpare register. this mode introduces additional hard- ware control, interrupting only on frames that match the uart?s address. when an incoming address byte does no t match the uart?s address, it is ignored. all successive data bytes in this frame are also ignored. wh en a matching address byte occurs, an inter- rupt is issued and further inte rrupts now occur on each successi ve data byte. when the first data byte in the frame is read, the newfrm bit of the uart status 1 register is asserted. all successive data bytes have newfrm = 0. when the next addre ss byte occurs, the hard- ware compares it to the uart?s address. if there is a match, the interrupts continues and the newfrm bit is set for the first byte of the ne w frame. if there is no match, the uart ignores all incoming bytes un til the next address match. the third scheme is enable d by setting mpmd[1:0] to 11b and by writing the uart?s address into the uart address co mpare register. this mode is identical to the second
ps024315-1011 p r e l i m i n a r y operation z8 encore! xp ? f0823 series product specification 105 scheme, except that there are no interrupts on address bytes. the first data byte of each frame remains accompanied by a newfrm assertion. external driver enable the uart provides a driver enable (de) si gnal for off-chip bus transceivers. this fea- ture reduces the software overhead associated with using a gpio pin to control the trans- ceiver when communicatin g on a multi-transceiver bus, such as rs-485. driver enable is an active high signal that envelopes the entire transmitted data frame including parity and stop bits as displayed in figure 14. the driver enable signal asserts when a byte is written to the uart transm it data register. the driver enable signal asserts at least one uart bit period and no greater than two uart bit periods before the start bit is transmitted. this allows a setup time to enable the transceiver. the driver enable signal deasserts one system clock period after the final stop bit is transmitted. this one system clock delay allows both time for da ta to clear the transc eiver before disabling it, as well as the ability to determine if another character follows the current character. in the event of back to back char acters (new data must be written to the transmit data regis- ter before the previous character is completely transmitted) the de signal is not deasserted between characters. the depol bit in the uart control regist er 1 sets the polarity of the driver enable signal. the driver enable to start bit setup time is calculated as follows: uart interrupts the uart features separate interrupts for the transmitter and the rece iver. in addition, when the uart primary functionality is disabled, the baud rate generator can also func- tion as a basic timer with interrupt capability. figure 14. uart driver enable signal timing (shown with 1 stop bit and parity) start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity data field lsb msb idle state of line stop bit 1 1 0 0 1 de
ps024315-1011 p r e l i m i n a r y operation z8 encore! xp ? f0823 series product specification 106 transmitter interrupts the transmitter generates a single interrupt when the transmit data register empty bit ( tdre ) is set to 1. this indicates that the tran smitter is ready to accept new data for trans- mission. the tdre interrupt occurs after the transmit shift register has shifted the first bit of data out. the transmit data register can now be written with the next character to send. this action provides 7 bit periods of la tency to load the transmit data register before the transmit shift register completes shifting the current character. writing to the uart transmit data register clears the tdre bit to 0. receiver interrupts the receiver generates an interrupt when any of the following occurs: ? a data byte is received and is available in the uart receive data register. this inter- rupt can be disabled independently of the other receiver interrupt sources. the received data interrupt occurs after the receive character has been received and placed in the re- ceive data register. to avoid an overrun erro r, software must respond to this received data available condition before the next character is completely received. in multiprocessor mode ( mpen = 1), the receive data interrupts are dependent on the multiprocessor configuration and the most recent address byte. ? a break is received ? an overrun is detected ? a data framing error is detected uart overrun errors when an overrun error conditio n occurs the uart prevents overwriting of the valid data currently in the receive data register. the br eak detect and overrun status bits are not displayed until after the va lid data has been read. after the valid data has been read, the uart st atus 0 register is updated to indicate the overrun condition (and break de tect, if applicable). the rda bit is set to 1 to indicate that the receive data register contains a data byte. however, because the overrun error 1 baud rate (hz) ---------------------------------------- - ?? ?? de to start bit setup time (s) 2 baud rate (hz) ---------------------------------------- - ?? ?? ?? note:
ps024315-1011 p r e l i m i n a r y operation z8 encore! xp ? f0823 series product specification 107 occurred, this byte cannot contain valid data and must be ignored. the brkd bit indicates if the overrun was caused by a break condition on the line. after reading the status byte indicating an overrun error, the receive data re gister must be read again to clear the error bits is the uart status 0 register. updates to the receive data register occur only when the next data word is received. uart data and error handling procedure figure 15 displays the recommended procedur e for use in uart receiver interrupt service routines. figure 15. uart receiver in terrupt service routine flow receiver errors? no yes read status discard data read data which interrupt receiver ready clears rda bit and resets error bits read data
ps024315-1011 p r e l i m i n a r y uart control register definitions z8 encore! xp ? f0823 series product specification 108 baud rate gene rator interrupts if the baud rate generator (brg) interrupt en able is set, the uart receiver interrupt asserts when the uart baud rate generator reloads. this conditio n allows the baud rate generator to function as an additional counter if the uart functionality is not employed. uart baud ra te generator the uart baud rate generator creates a lowe r frequency baud rate clock for data trans- mission. the input to the baud rate generator is the system clock. the uart baud rate high and low byte registers combine to cr eate a 16-bit baud rate divisor value (brg[15:0]) that sets the data transmission rate (baud rate) of the uart. the uart data rate is calculated usin g the following equation: when the uart is disabled, the baud rate generator functions as a basic 16-bit timer with interrupt on time-out. observe the following steps to configure the baud rate gener- ator as a timer with interrupt on time-out: 1. disable the uart by clearing the ren and ten bits in the uart control 0 register to 0. 2. load the acceptable 16-bit count value into the uart ba ud rate high and low byte registers. 3. enable the baud rate generator timer fu nction and associated interrupt by setting the birq bit in the uart control 1 register to 1. ? when configured as a general purpose timer, th e interrupt interval is calculated using the following equation: uart control register definitions the uart control registers support the uart and the associated infrared encoder/decod- ers. for more information about the infrared operation, see the infrared encoder/decoder chapter on page 117. uart data rate (bits/s) system clock frequency (hz) 16 uart baud rate divisor value ? -------------------------------------------------------------------------------- - = interrupt interval (s) syste m clock period (s) brg[15:0] ? =
ps024315-1011 p r e l i m i n a r y uart control register definitions z8 encore! xp ? f0823 series product specification 109 uart transmit data register data bytes written to the uart transmit data register (table 64) are shifted out on the txdx pin. the write-only uart transmit data register shares a register file address with the read-only uart receive data register. uart receive data register data bytes received through the rxd x pin are stored in the uart receive data register (table 65). the read-only uart receive data register shares a register file address with the write-only uart transmit data register. table 64. uart transmit data register (u0txd) bit 7 6 5 4 3 2 1 0 field txd reset xxxxxxxx r/w wwwwwwww address f40h bit description [7:0] ? txd transmit data uart transmitter data byte to be shifted out through the txd x pin. table 65. uart receive data register (u0rxd) bit 7 6 5 4 3 2 1 0 field rxd reset xxxxxxxx r/w rrrrrrrr address f40h bit description [7:0] ? rxd receive data uart receiver data byte from the rxd x pin.
ps024315-1011 p r e l i m i n a r y uart control register definitions z8 encore! xp ? f0823 series product specification 110 uart status 0 register the uart status 0 and status 1 registers (t able 66 and table 67) identify the current uart operating configuration and status. table 66. uart status 0 register (u0stat0) bit 7 6 5 4 3 2 1 0 field rda pe oe fe brkd tdre txe cts reset 0000011x r/w rrrrrrrr address f41h bit description [7] ? rda receive data available this bit indicates that the uart receive data register has received data. reading the uart receive data register clears this bit. 0 = the uart receive data register is empty. 1 = there is a byte in the uart receive data register. [6] ? pe parity error this bit indicates that a parity error has occurred. reading th e uart receive data ? register clears this bit. 0 = no parity error has occurred. 1 = a parity error has occurred. [5] ? oe overrun error this bit indicates that an overrun error has occurred. an overrun occurs when new data is received and the uart receive data register has not been read. if the rda bit is reset to 0, reading the uart receive data register clears this bit. 0 = no overrun error occurred. 1 = an overrun error occurred. [4] ? fe framing error this bit indicates that a framing error (no st op bit following data reception) was detected. reading the uart receive data register clears this bit. 0 = no framing error occurred. 1 = a framing error occurred. [3] ? brkd break detect this bit indicates that a break occurred. if the data bits, parity/multiprocessor bit, and stop bit(s) are all 0s this bit is se t to 1. reading the uart receive data register clears this bit. 0 = no break occurred. 1 = a break occurred.
ps024315-1011 p r e l i m i n a r y uart control register definitions z8 encore! xp ? f0823 series product specification 111 uart status 1 register this register contains multipro cessor control and status bits. [2] ? tdre transmitter data register empty this bit indicates that the uart transmit data register is empty and ready for additional data. writing to the uart transmit da ta register resets this bit. 0 = do not write to the uart transmit data register. 1 = the uart transmit data register is ready to receive an additional byte to be transmitted. [1] ? txe transmitter empty this bit indicates that the transmit shift register is empty and character transmission is finished. 0 = data is curren tly transmitting. 1 = transmission is complete. [0] ? cts cts signal when this bit is read, it returns the level of the cts signal. this signal is active low. table 67. uart status 1 register (u0stat1) bit 7 6 5 4 3 2 1 0 field reserved newfrm mprx reset 00000000 r/w rrrrr/wr/wrr address f44h bit description [7:2] reserved these bits are reserved; r/w bits must be programmed to 000000 during writes and 000000 when read. [1] ? newfrm new frame a status bit denoting the start of a new frame. reading the uart receive data register resets this bit to 0. 0 = the current byte is not the first data byte of a new frame. 1 = the current byte is the first data byte of a new frame. [0] ? mprx multiprocessor receive returns the value of the most recent multip rocessor bit received. reading from the uart receive data register resets this bit to 0. bit description (continued)
ps024315-1011 p r e l i m i n a r y uart control register definitions z8 encore! xp ? f0823 series product specification 112 uart control 0 and control 1 registers the uart control 0 and control 1 registers (table 68 and table 69) configure the ? properties of the uart?s transmit and recei ve operations. the uar t control registers must not be written while the uart is enabled. table 68. uart control 0 register (u0ctl0) bit 7 6 5 4 3 2 1 0 field ten ren ctse pen psel sbrk stop lben reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f42h bit description [7] ? ten transmit enable this bit enables or disables the transmitter. the enable is also controlled by the cts signal and the ctse bit. if the cts signal is low and the ctse bit is 1, the transmitter is enabled. 0 = transmitter disabled. 1 = transmitter enabled. [6] ? ren receive enable this bit enables or disables the receiver. 0 = receiver disabled. 1 = receiver enabled. [5] ? ctse ctse?cts enable 0 = the cts signal has no effect on the transmitter. 1 = the uart recognizes the cts signal as an enable control from the transmitter. [4] ? pen parity enable this bit enables or disables parity. even or odd is determined by the psel bit. 0 = parity is disabled. 1 = the transmitter sends data with an additional parity bit and the receiver receives an addi- tional parity bit . [3] ? psel parity select 0 = even parity is transmitted and expected on all received data. 1 = odd parity is transmitted and expected on all received data. [2] ? sbrk send break this bit pauses or breaks data transmission. sending a break interrupts any transmission in progress, so ensure that the transmitter has fi nished sending data before setting this bit. 0 = no break is sent. 1 = forces a break condition by setting the output of the transmitter to zero.
ps024315-1011 p r e l i m i n a r y uart control register definitions z8 encore! xp ? f0823 series product specification 113 [1] ? stop stop bit select 0 = the transmitter sends one stop bit. 1 = the transmitter sends two stop bits. [0] ? lben loop back enable 0 = normal operation. 1 = all transmitted data is lo oped back to the receiver. table 69. uart control 1 register (u0ctl1) bit 7 6 5 4 3 2 1 0 field mpmd[1] mpen mpmd[0] mpbt depol brgctl rdairq iren reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f43h bit description [7,5] ? mpmd[1:0] multiprocessor mode if multiprocessor (9-b it) mode is enabled. 00 = the uart generates an interrupt request on all received bytes (data and address). 01 = the uart generates an interrupt request only on received address bytes. 10 = the uart generates an interrupt request when a received address byte matches the value stored in the address compare register and on all successive data bytes until an address mismatch occurs. 11 = the uart generates an interrupt request on all received data bytes for which the most recent address byte matched the val ue in the address compare register. [6] ? mpen multiprocessor (9-bit) enable this bit is used to enable multiprocessor (9-bit) mode. 0 = disable multiprocessor (9-bit) mode. 1 = enable multiprocessor (9-bit) mode. [4] ? mpbt multiprocessor bit transmit this bit is applicable only when multiprocesso r (9-bit) mode is enabled. the 9th bit is used by the receiving device to determine if the data byte contains address or data informa- tion. 0 = send a 0 in the multiprocessor bit location of the data stream (data byte). 1 = send a 1 in the multiprocessor bit location of the data stream (address byte). [3] ? depol driver enable polarity 0 = de signal is active high. 1 = de signal is active low. bit description (continued)
ps024315-1011 p r e l i m i n a r y uart control register definitions z8 encore! xp ? f0823 series product specification 114 [2] ? brgctl baud rate control this bit causes an alternate uart behavior dep ending on the value of the ren bit in the uart control 0 register. when the uart receiver is not enabled (ren=0), this bit determines whether the baud rate generator i ssues interrupts. 0 = reads from the baud rate high and low byte registers return the brg reload value. 1 = the baud rate generator generates a receive interrupt when it counts down to 0. ? reads from the baud rate high and low byte registers return the current brg count value. when the uart receiver is enabled (ren=1), th is bit allows reads fr om the baud rate reg- isters to return the brg count value instead of the reload value. 0 = reads from the baud rate high and low byte registers return the brg reload value. 1 = reads from the baud rate high and low byte registers return the current brg count value. unlike the timers, there is no mech anism to latch the low byte when the high byte is read. [1] ? rdairq receive data interrupt enable 0 = received data and receiver errors generates an interrupt request to the interrupt con- troller. 1 = received data does not generate an interrupt request to the interrupt controller. only receiver errors generate an interrupt request. [0] ? iren infrared encoder/decoder enable 0 = infrared encoder/decoder is disabled. uart operates normally. 1 = infrared encoder/decoder is enabled. the uart transmits and receives data through the infrared encoder/decoder. bit description (continued)
ps024315-1011 p r e l i m i n a r y uart control register definitions z8 encore! xp ? f0823 series product specification 115 uart address compare register the uart address compare register stores th e multinode network address of the uart. when the mpmd[1] bit of uart control register 0 is set, all incoming address bytes are compared to the value stored in the address compare register. receive interrupts and rda assertions only occur in the event of a match. uart baud rate high and low byte registers the uart baud rate high and low byte regi sters (table 71 and table 72) combine to create a 16-bit baud rate divisor value (brg[15:0]) that sets the data transmission rate (baud rate) of the uart. table 70. uart address co mpare register (u0addr) bit 7 6 5 4 3 2 1 0 field comp_addr reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f45h bit description [7:0] ? comp_addr compare address this 8-bit value is compared to incoming address bytes. table 71. uart baud rate hi gh byte register (u0brh) bit 7 6 5 4 3 2 1 0 field brh reset 11111111 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f46h table 72. uart baud rate low byte register (u0brl) bit 7 6 5 4 3 2 1 0 field brl reset 11111111 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f47h
ps024315-1011 p r e l i m i n a r y uart control register definitions z8 encore! xp ? f0823 series product specification 116 the uart data rate is calcula ted using the following equation: for a given uart data rate, calcu late the integer baud rate di visor value using the follow- ing equation: the baud rate error relative to the acceptable baud rate is calculated usin g the following equation: for reliable communication, the uart baud rate error must never exceed five percent. table 73 provides information about data rate errors for a 5.5296 mhz system clock. table 73. uart baud rates 5.5296 mhz system clock acceptable rate (khz) brg divisor (decimal) actual rate (khz) error (%) 1250.0 n/a n/a n/a 625.0 n/a n/a n/a 250.0 1 345.6 38.24 115.2 3 115.2 0.00 57.6 6 57.6 0.00 38.4 9 38.4 0.00 19.2 18 19.2 0.00 9.60 36 9.60 0.00 4.80 72 4.80 0.00 2.40 144 2.40 0.00 1.20 288 1.20 0.00 0.60 576 0.60 0.00 0.30 1152 0.30 0.00 uart baud rate (bits/s) system clock frequency (hz) 16 uart baud rate divisor value ? ------------------- ------------------------------------------- ------------------ - = uart baud rate divisor value (brg) round system clock frequency (hz) 16 uart data rate (bits/s) ? --------------- ----------------------------------- --------------- - ?? ?? = uart baud rate error (%) 100 actual data rate desired data rate ? desired data rate ------------------------------------------------------------------------------------ - ?? ?? ? =
ps024315-1011 p r e l i m i n a r y infrared encoder/decoder z8 encore! xp ? f0823 series product specification 117 infrared encoder/decoder z8 encore! xp f0823 series products contai n a fully-functional, high-performance uart with an infrared encoder/decode r (endec). the infrared endec is integrated with an on-chip uart to allow easy communica tion between the z8 encore! xp and irda physical layer specification, version 1.3-compliant infrare d transceivers. infrared communication pro- vides secure, reliable, low-co st, point-to-point communica tion between pcs, pdas, cell phones, printers and other infrared enabled devices. architecture figure 16 displays the architecture of the infrared endec. operation when the infrared endec is enabled, the tr ansmit data from the associated on-chip uart is encoded as digital signals in accordance with the irda standard and output to the infra- red transceiver through the txd pin. similarly, data received from the infrared transceiver is passed to the infrared endec through the rxd pin, decoded by the infrared endec, and figure 16. infrared data communication system block diagram interrupt signal rxd txd infrared encoder/decoder uart rxd txd system clock i/o address data infrared transceiver rxd txd baud rate clock (endec)
ps024315-1011 p r e l i m i n a r y operation z8 encore! xp ? f0823 series product specification 118 passed to the uart. communication is hal f-duplex, which means simultaneous data transmission and reception is not allowed. the baud rate is set by the uart?s baud rate generator and supports irda standard baud rates from 9600 baud to 115.2 kbaud. higher baud rates are possible, but do not meet irda specifications. the uart must be enabled to use the infrared endec. the infrared endec data rate is calculated us ing the following equation: transmitting irda data the data to be transmitted using the infrared transceiver is first se nt to the uart. the uart?s transmit signal (txd) and baud rate clock are used by the irda to generate the modulation signal (ir_txd) that drives th e infrared transceiver. each uart/infrared data bit is 16 clocks wide. if the data to be transmitted is 1, the ir_txd signal remains low for the full 16 clock period. if the data to be transmitted is 0, the transmitter first out- puts a 7 clock low period, followed by a 3 clock high pulse. finally, a 6 clock low pulse is output to complete the full 16 clock data pe riod. figure 17 displays irda data transmis- sion. when the infrared endec is enabled, the uart?s txd signal is internal to z8 encore! xp f0823 series produc ts while the ir_txd signal is output through the txd pin. figure 17. infrared data transmission infrared data rate (bits/s) system clock frequency (hz) 16 uart baud rate divisor value ? ------------------- ------------------------------------------ ------------------- - = baud rate ir_txd uart?s 16 clock period start bit = 0 data bit 0 = 1 data bit 1 = 0 data bit 2 = 1 data bit 3 = 1 7-clock delay 3 clock pulse txd clock
ps024315-1011 p r e l i m i n a r y operation z8 encore! xp ? f0823 series product specification 119 receiving irda data data received from the infrare d transceiver using the ir_rxd signal through the rxd pin is decoded by the infrared endec and passed to the uart. the uart?s baud rate clock is used by the infrared endec to generate the demodulated si gnal (rxd) that drives the uart. each uart/infrared data bit is 16-clock s wide. figure 18 displays data reception. when the infrared endec is enab led, the uart?s rxd signal is internal to the z8 encore! xp f0823 series products wh ile the ir_rxd signal is received through the rxd pin. infrared data reception the system clock frequency must be at least 1.0 mhz to ensure proper reception of the 1.4 s minimum width pulses allowed by the irda standard. endec receiver synchronization the irda receiver uses a local baud rate clock co unter (0 to 15 clock periods) to generate an input stream for the uart and to create a sampling window for detection of incoming pulses. the generated uart input (uart rxd) is delayed by 8 baud rate clock periods with respect to the incoming irda data stream. when a fa lling edge in the input data stream is detected, the endec counter is reset . when the count reaches a value of 8, the uart rxd value is updated to reflect the va lue of the decoded data. when the count reaches 12 baud clock periods, the sampling window for the next incoming pulse opens. figure 18. irda data reception baud rate uart?s ir_rxd 16 clock period start bit = 0 data bit 0 = 1 data bit 1 = 0 data bit 2 = 1 data bit 3 = 1 8 clock delay clock rxd 16 clock period 16 clock period 16 clock period 16 clock period start bit = 0 data bit 0 = 1 data bit 1 = 0 data bit 2 = 1 data bit 3 = 1 min. 1.4 ? s pulse caution:
ps024315-1011 p r e l i m i n a r y infrared encoder/decoder control register z8 encore! xp ? f0823 series product specification 120 the window remains open until th e count again reaches 8 (that is, 24 baud clock periods since the previous pulse was detected), givi ng the endec a sampling window of minus four baud rate clocks to plus eight baud rate clocks around the expected time of an incoming pulse. if an incoming pulse is detected inside this window th is process is repeated. if the incoming data is a logical 1 (no pulse), the endec returns to the initial state and waits for the next falling edge. as each falling edge is dete cted, the endec clock counter is reset, resynchronizing the endec to th e incoming signal, allowing the endec to tolerate jitter and baud rate errors in the incoming datastream. resynchron izing the endec does not alter the operation of the uart, which ultimately re ceives the data. the uart is only synchro- nized to the incoming data str eam when a start bit is received. infrared encoder/decoder co ntrol register definitions all infrared endec configuration and status in formation is set by the uart control regis- ters as defined in the universal asynchronous receiver/transmitter chapter on page 97. to prevent spurious signals during irda data transmission, set the iren bit in the uart control 1 register to 1 to en able the endec before enabling the gpio port alternate func- tion for the corresponding pin. caution:
ps024315-1011 p r e l i m i n a r y analog-to-digital converter z8 encore! xp ? f0823 series product specification 121 analog-to-digital converter the analog-to-digital converter (adc) converts an analog input signal to its digital rep- resentation. the features of this sigma-delta adc include: ? 10-bit resolution ? eight single-ended analog input sources are multiplexed with general-purpose i/o ports ? interrupt upon conversion complete ? bandgap generated internal voltage refere nce generator with two selectable levels ? factory offset and gain calibration architecture figure 19 displays the major functional bl ocks of the adc. an analog multiplexer net- work selects the adc inpu t from the available analog pins, ana0 through ana7.
ps024315-1011 p r e l i m i n a r y operation z8 encore! xp ? f0823 series product specification 122 operation the output of the adc is an 11-bit, signed, two?s-complement digital value. the output generally ranges from 0 to +1023, but offs et errors can cause small negative values. the adc registers return 13 bits of data, bu t the two lsbs are inte nded for compensation use only. when the co mpensation routine is performed on the 13 bit raw adc value, two bits of resolution are lost because of a rounding error. as a result, the final value is an 11- bit number. figure 19. analog-to-digital converter block diagram analog input multiplexer internal voltage reference generator analog input ref input v ref adc irq adc data v refsel 2 11 ana7 ana6 ana5 ana4 ana3 ana2 ana1 ana0 vrefext anain 4
ps024315-1011 p r e l i m i n a r y operation z8 encore! xp ? f0823 series product specification 123 automatic powerdown if the adc is idle (no conversions in progre ss) for 160 consecutive system clock cycles, portions of the adc are automatically powe red down. from this powerdown state, the adc requires 40 system clock cycles to powerup. the adc powers up when a conversion is requested by the adc control register. single-shot conversion when configured for single-shot conversion, the adc performs a single analog-to-digital conversion on the selected analog input chan nel. after completion of the conversion, the adc shuts down. observe the following step s for setting up the adc and initiating a sin- gle-shot conversion: 1. enable the acceptable analog inputs by co nfiguring the general-purpose i/o pins for alternate function. this configuration disa bles the digital input and output drivers. 2. write the adc control/status register 1 to configure the adc ? write the refselh bit of the pair { refselh , refsell } to select the internal voltage reference level or to disa ble the internal reference. the refselh bit is contained in the adc co ntrol/status register 1. ? 3. write to the adc control register 0 to configure the adc and begin the conversion. the bit fields in the adc control re gister can be written simultaneously: ? write to the anain[3:0] field to select from the available analog input sources (different input pins available depending on the device). ? clear cont to 0 to select a single-shot conversion. ? if the internal voltage reference mu st be output to a pin, set the refext bit to 1. the internal voltage reference must be enabled in this case. ? write the refsell bit of the pair { refselh , refsell } to select the internal voltage reference level or to disable the internal reference. the refsell bit is contained in the adc control register 0. ? set cen to 1 to start the conversion. ? 4. cen remains 1 while the conversion is in progress. a single-shot conversion requires 5129 system clock cycles to complete. if a single-shot conversion is requested from an adc powered-down state, the adc uses 40 additional clock cycles to power-up before beginning the 5129 cycle conversion. 5. when the conversion is co mplete, the adc control logi c performs the following oper- ations: ? 11-bit two?s-complement result written to {adcd_h[7:0], adcd_l[7:5]}
ps024315-1011 p r e l i m i n a r y operation z8 encore! xp ? f0823 series product specification 124 ? cen resets to 0 to indicate the conversion is complete ? 6. if the adc remains idle for 160 consecutive system clock cycles, it is automatically powered-down. continuous conversion when configured for continuous conversion , the adc continuously performs an analog- to-digital conversion on the sel ected analog input. each new data value over-writes the previous value stored in the adc data register s. an interrupt is generated after each con- version. in continuous mode, adc updates are limited by the input signal bandwidth of the adc and the latency of the adc and its digital filter. step changes at the input are not detected at the next output from the adc. th e response of the adc (in all modes) is lim- ited by the input signal bandwidth and the latency. observe the following steps fo r setting up the adc and initia ting continuous conversion: 1. enable the acceptable analog input by conf iguring the general-purpose i/o pins for alternate function. this action disables the digital input and output driver. 2. write the adc control/status register 1 to configure the adc: ? write the refselh bit of the pair { refselh , refsell } to select the internal voltage reference level or to disable the internal reference. the refselh bit is contained in the adc co ntrol/status register 1. ? 3. write to the adc control register 0 to co nfigure the adc for continuous conversion. the bit fields in the adc control re gister can be written simultaneously: ? write to the anain[3:0] field to select from the available analog input sources (different input pins available depending on the device). ? set cont to 1 to select continuous conversion. ? if the internal vref must be output to a pin, set the refext bit to 1. the inter- nal voltage reference must be enabled in this case. ? write the refsell bit of the pair {refselh, refsell} to select the internal voltage reference level or to disable the internal reference. the refsell bit is contained in adc control register 0. ? set cen to 1 to start the conversions. ? caution:
ps024315-1011 p r e l i m i n a r y operation z8 encore! xp ? f0823 series product specification 125 4. when the first conversion in continuous operation is complete (after 5129 system clock cycles, plus the 40 cycles for powe r-up, if necessary), the adc control logic performs the following operations: ? cen resets to 0 to indicate the first conversion is complete. cen remains 0 for all subsequent conversions in continuous operation ? an interrupt request is sent to the interru pt controller to indicate the conversion is complete ? 5. the adc writes a new data result every 256 system clock cycles. for each completed conversion, the adc control logic performs the following operations: ? writes the 11-bit two?s complement result to {adcd_h[7:0], adcd_l[7:5]} ? an interrupt request to the interrupt controller denoting co nversion complete ? 6. to disable continuous conversion, clear the cont bit in the adc control register to 0. interrupts the adc is able to interrupt the cpu whenev er a conversion has been completed and the adc is enabled. when the adc is disabled, an interrupt is not asserted; however, an interrupt pending when the adc is disabled is not cleared. calibration and compensation z8 encore! xp f0823 series adc can be factory calibrated for offset error and gain error, with the compensation data stored in flash me mory. alternatively, user code can perform its own calibration, storing the values into flash themselves. factory calibration devices that have been factory calibrated co ntain nine bytes of calibration data in the flash option bit space. this data consists of three bytes for each re ference type. for a list of input modes for which calib ration data exists, see the zilog calibration data section on page 152. there is 1 byte for offset, and there are 2 bytes for gain correction. user calibration if you have precision references available, its own external calibration can be performed, storing the values into flash themselves.
ps024315-1011 p r e l i m i n a r y adc control register definitions z8 encore! xp ? f0823 series product specification 126 software compensation procedure the value read from the adc high and low by te registers are uncompensated. the user mode software must apply gain and offset correction to this un compensated value for maximum accuracy. the following form ula yields the compensated value: where gaincal is the gain calibration byte, offcal is the offset calibration byte and adc uncomp is the uncompensated value read fro m the adc. the offcal value is in two?s complement format, as are the compensated and uncompensated adc values. the offset compensation is performed first, fo llowed by the gain compensation. one bit of resolution is lost because of rounding on both the offset and gain co mputations. as a result the adc registers read back 13 bits: 1 sign bit, two calibration bits lost to rounding and 10 data bits. also note that in the second term, the multiplicati on must be performed before the division by 2 16 . otherwise, the second term evaluates to zero incorrectly. although the adc can be used without the gain and offset compensation, it does exhibit non-unity gain. designing the adc with su b-unity gain reduces noise across the adc range but requires the adc results to be scaled by a factor of 8/7. adc control register definitions the following sections define the adc control registers. adc control register 0 the adc control register selects the analog input channel and initia tes the analog-to-dig- ital conversion. adc comp adc uncomp offcal ? ?? adc uncomp offcal ? ?? ? gaincal ?? 2 1 ? + = note: caution:
ps024315-1011 p r e l i m i n a r y adc control register definitions z8 encore! xp ? f0823 series product specification 127 table 74. adc control register 0 (adcctl0) bit 7 6 5 4 3 2 1 0 field cen refsell refext cont anain[3:0] reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f70h bit description [7] ? cen conversion enable 0 = conversion is complete. writing a 0 produces no effect. the adc automatically clears this bit to 0 when a conversion is complete. 1 = begin conversion. writing a 1 to this bit star ts a conversion. if a conversion is already in progress, the conversion restarts. this bit remains 1 until the conversion is complete. [6] ? refsell voltage reference level select low bit in conjunction with the high bit (refselh) in adc control/status regi ster 1, this deter- mines the level of the internal voltage refere nce; the following details the effects of {ref- selh, refsell}. this reference is independent of the comparator reference. 00 = internal reference disabled, reference comes from external pin. 01 = internal reference set to 1.0 v. 10 = internal reference set to 2.0 v (default). [5] ? refext external reference select 0 = external reference buffer is disabled; v ref pin is available for gpio functions. 1 = the internal adc reference is buffered and connected to the v ref pin. [4] ? cont continuous conversion 0 = single-shot conversion. adc data is output once at completion of the 5129 system clock cycles. 1 = continuous conversion. adc data updated every 256 system clock cycles.
ps024315-1011 p r e l i m i n a r y adc control register definitions z8 encore! xp ? f0823 series product specification 128 [3:0] ? anain analog input select these bits select the analog input for conversion. not all port pins in this list are available in all packages for z8 encore! xp f0823 series. for information about the port pins available with each package style, see the pin description section on page 7. do not enable unavail- able analog inputs. usage of these bits changes depending on the buffer mode selected in adc control/status register 1. for the reserved values, all input switches are disabled to avoid leakage or other undesir- able operation. adc samples taken with reserved bit settings are undefined. single-ended: 0000 = ana0. ? 0001 = ana1. ? 0010 = ana2. ? 0011 = ana3. ? 0100 = ana4. ? 0101 = ana5. ? 0110 = ana6. ? 0111 = ana7. ? 1000 = reserved. ? 1001 = reserved. ? 1010 = reserved. ? 1011 = reserved. ? 1100 = reserved. ? 1101 = reserved. ? 1110 = reserved. ? 1111 = reserved. bit description (continued)
ps024315-1011 p r e l i m i n a r y adc control register definitions z8 encore! xp ? f0823 series product specification 129 adc control/status register 1 the second adc control register contains the voltage reference level selection bit. table 75. adc control/status register 1 (adcctl1) bit 7 6 5 4 3 2 1 0 field refselh reserved reset 10000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f71h bit description [7] ? refselh voltage reference level select high bit in conjunction with the low bit (refsell) in adc control register 0, this bit determines the level of the internal voltage reference; the following details the effects of {refselh, refsell}; this reference is independent of the comparator reference. 00 = internal reference disabled, reference comes from external pin. 01 = internal reference set to 1.0 v. ? 10 = internal reference set to 2.0 v (default). [6:0] reserved these bits are reserved and must be programmed to 0000000.
ps024315-1011 p r e l i m i n a r y adc control register definitions z8 encore! xp ? f0823 series product specification 130 adc data high byte register the adc data high byte regist er contains the upper eight bits of the adc output. the output is an 11-bit two?s comple ment value. during a single-sh ot conversion, this value is invalid. access to the adc data high byte re gister is read-only. reading the adc data high byte register latches data in the adc low bits register. table 76. adc data high byte register (adcd_h) bit 7 6 5 4 3 2 1 0 field adcdh reset xxxxxxxx r/w rrrrrrrr address f72h bit description [7:0] ? adcdh adc data high byte this byte contains the upper eight bits of the adc output. these bits are not valid during a sin- gle-shot conversion. during a continuous conversion, the most recent conversion output is held in this register. these bits are undefined after a reset.
ps024315-1011 p r e l i m i n a r y adc control register definitions z8 encore! xp ? f0823 series product specification 131 adc data low bits register the adc data low byte register contains the lower bits of the adc output as well as an overflow status bit. the output is a 11-bit two?s complement value. during a single-shot conversion, this value is invalid. access to th e adc data low byte register is read-only. reading the adc data high byte register la tches data in the adc low bits register. table 77. adc data low bits register (adcd_l) bit 7 6 5 4 3 2 1 0 field adcdl reserved ovf reset xxxxxxxx r/w rrrrrrrr address f73h bit description [7:5] ? adcdl adc data low bits these bits are the least significant three bits of the 11-bits of the adc output. these bits are undefined after a reset. [4:1] reserved these bits are reserved and are undefined when read. [0] ? ovf overflow status 0 = an overflow did not occur in the digital filter for the current sample. 1 = an overflow did occur in the digital filter for the current sample.
ps024315-1011 p r e l i m i n a r y comparator z8 encore! xp ? f0823 series product specification 132 comparator z8 encore! xp f0823 series devices feature a general purpose comparator that compares two analog input signals. a gpio ( cinp ) pin provides the positive comparator input. the negative input ( cinn ) can be taken from either an extern al gpio pin or an internal refer- ence. the output is available as an interrupt source or can be routed to an external pin using the gpio multiplex. the features of the comparator include: ? two inputs which can be connected up using the gpio multiplex (mux) ? one input can be connected to a programmable internal reference ? one input can be connected to the on-chip temperature sensor ? output can be either an interrupt sour ce or an output to an external pin operation one of the comparator inputs can be connecte d to an internal reference which is a user selectable reference that is user pr ogrammable with 200 mv resolution. the comparator can be powered down to sa ve on supply current. for details, see the power control register 0 section on page 31. because of the propagation delay of the co mparator, zilog does not recommend enabling or reconfiguring the comparat or without first disabling the interrupts and wa iting for the comparator output to settle. doing so can result in spurious interrupts. the following example shows how to safely enable the comparator: di ld cmp0 nop nop ; wait for output to settle clr irq0 ; clear any spurious interrupts pending ei caution:
ps024315-1011 p r e l i m i n a r y comparator control register definition z8 encore! xp ? f0823 series product specification 133 comparator control register definition the comparator control register (cmpctl) co nfigures the comparator inputs and sets the value of the internal voltage reference. table 78. comparator control register (cmp0) bit 7 6 5 4 3 2 1 0 field inpsel innsel reflvl reserved reset 00010100 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f90h bit description [7] ? inpsel signal select for positive input 0 = gpio pin used as positive comparator input. 1 = temperature sensor used as positive comparator input. [6] ? innsel signal select for negative input 0 = internal reference disabled, gpio pin used as negative comparator input. 1 = internal reference enabled as negative comparator input. [5:2] ? reflvl internal reference voltage level 0000 = 0.0 v. ? 0001 = 0.2 v. ? 0010 = 0.4 v. ? 0011 = 0.6 v. ? 0100 = 0.8 v. ? 0101 = 1.0 v (default). ? 0110 = 1.2 v. ? 0111 = 1.4 v. ? 1000 = 1.6 v. ? 1001 = 1.8 v. ? 1010?1111 = reserved. note: this reference is independent of the adc voltage reference. [1:0] reserved these bits are reserved; r/w bits must be pr ogrammed to 00 during writes and to 00 when read.
ps024315-1011 p r e l i m i n a r y flash memory z8 encore! xp ? f0823 series product specification 134 flash memory the products in z8 encore! xp f0823 series features either 8 kb (8192), 4 kb (4096), 2 kb (2048) or 1 kb (1024) of nonvolatile flash memory with read/write/erase capability. flash memory can be programmed and erased in-c ircuit by either user code or through the on-chip debugger. the flash memory array is arranged in pages with 512 bytes per page. the 512-byte page is the minimum flash block size that can be era sed. each page is divided into 8 rows of 64 bytes. for program/data protection, the flash memory is also divided into sectors. in the z8 encore! xp f0823 series, these sectors are either 1024 bytes (in the 8 kb devices) or 512 bytes in size (all other memory sizes); each sector maps to a page. page and sector sizes are not generally equal. the first two bytes of the flash program memo ry are used as flash option bits. for more information about their operation, see the flash option bits chapter on page 146. table 79 describes the flash memory configuration for each device in the z8 encore! xp f0823 series. figure 20 displays the flash memory arrangement. table 79. z8 encore! xp f0823 series flash memory configurations part number flash size kb (bytes) flash pages program memory addresses flash sector size (bytes) z8f08x3 8 (8192) 16 0000h?1fffh 1024 z8f04x3 4 (4096) 8 0000h?0fffh 512 z8f02x3 2 (2048) 4 0000h?07ffh 512 z8f01x3 1 (1024) 2 0000h?03ffh 512
ps024315-1011 p r e l i m i n a r y flash information area z8 encore! xp ? f0823 series product specification 135 flash information area the flash information area is separate fro m program memory and is mapped to the address range fe00h to ffffh . not all these addresses are accessible. factory trim values for the analog peripherals are stored here. factory calibration data for the adc is also stored here. operation the flash controller programs and erases fl ash memory. the flash controller provides the proper flash controls and timing for byte programming, page erase, and mass erase of flash memory. the flash controller contains several protection mechanisms to prevent accidental program- ming or erasure. these mechanism operate on the page, sector and full-memory levels. figure 21 displays a basic flash controlle r flow. the following subsections provide details about the various oper ations (lock, unlock, byte programming, page protect, page unprotect, page select page erase, and mass erase) displayed in figure 21. figure 20. flash memory arrangement
ps024315-1011 p r e l i m i n a r y operation z8 encore! xp ? f0823 series product specification 136 figure 21. flash controller operation flowchart reset page 73h no yes 8ch no yes program/erase enabled 95h no yes write fctl lock state 0 lock state 1 write fctl write fctl byte program page erase write page select register write page select register page in no no unlocked protected sector? writes to page select register in lock state 1 result in a return to lock state 0 page select yes values match? yes
ps024315-1011 p r e l i m i n a r y operation z8 encore! xp ? f0823 series product specification 137 flash operation timing using the flash freq uency registers before performing either a program or erase operation on flash memory, you must first configure the flash frequency high and low byte registers. the flash frequency regis- ters allow programming and erasing of the fl ash with system clock frequencies ranging from 32 khz (32768 hz) through 20 mhz. the flash frequency high and low byte registers combine to form a 16-bit value, ffreq , to control timing for flash program and erase operations. the 16-bit binary flash fre- quency value must contain the system clock frequency (in khz). this value is calculated using the following equation: flash programming and erasure are not supp orted for system clock frequencies below 32 khz (32768 hz) or above 20 mhz. the flash frequency high and low byte registers must be loaded with the corr ect value to ensure operation of z8 encore! xp f0823 series devices. flash code protection against external access the user code contained within the flash memory can be protected against external access with the on-chip debugger. pr ogramming the frp flash optio n bit prevents reading of the user code with the on-chip debu gger. for more information, see the flash option bits section on page 146 and the on-chip debugger chapter on page 156. flash code protection agai nst accidental program and erasure f0823 series provides several levels of prot ection against accidental program and erasure of the flash memory contents. this protection is provided by a combination of the flash option bits, the register locking mechanism, the page select redundancy and the sector level protection control of the flash controller. flash code protection us ing the flash option bits the frp and fwp flash option bits combine to provide three levels of flash program memory protection as listed in table 80. for more info rmation, see the flash option bits section on page 146. ffreq[15:0] system clock frequency (hz) 1000 ------------------------------------------------------------------------------- = caution:
ps024315-1011 p r e l i m i n a r y operation z8 encore! xp ? f0823 series product specification 138 . flash code protection us ing the flash controller at reset, the flash controller locks to preven t accidental program or erasure of the flash memory. to program or erase the flash memory, first write the page select register with the target page. unlock the flash controlle r by making two consecutive writes to the flash control register with the values 73h and 8ch , sequentially. the page select regis- ter must be rewritten with the same page prev iously stored there. if the two page select writes do not match, the contro ller reverts to a locked state. if the two writes match, the selected page becomes active. for more details, see figure 21. after unlocking a specific page, you can enable either page program or erase. writing the value 95h causes a page erase only if the active page resides in a sector that is not pro- tected. any other value written to the flash co ntrol register locks the flash controller. mass erase is not allowed in the user co de but only in thro ugh the debug port. after unlocking a specific page, you can also wr ite to any byte on that page. after a byte is written, the page remains unlocked, allowing for subsequent writes to other bytes on the same page. further writes to the flash control register cause the active page to revert to a locked state. sector-based flash protection the final protection mechanism is implemente d on a per-sector basis. the flash memories of z8 encore! xp devices are divided into ma ximum number of 8 sectors. a sector is 1/8 of the total flash memory size unless this va lue is smaller than the page size ? in which case, the sector and page sizes are equal. on z8 encore! f0823 series devices, the sector size is varied according to the fl ash memory configuration shown in table 79 on page 134. the flash sector protect register can be co nfigured to prevent sectors from being pro- grammed or erased. after a sector is protected, it cannot be unprotected by user code. the flash sector protect register is cleared af ter reset, and any previously-written protection values are lost. user code must write this regi ster in their initialization routine if they pre- fer to enable sector protection. the flash sector protect register shares its register file address with the page select register. the flash sector protect register is accessed by writing the flash control regis- ter with 5eh . after the flash sector protect register is selected, it can be accessed at the page select register address. when user code writes the flash sector protect register, table 80. flash code protection using the flash option bits fwp flash code protection description 0 programming and erasing disabled for all of flash program memory. in user code program- ming, page erase, and mass erase are all disabled. mass erase is available through the on- chip debugger. 1 programming, page erase, and mass erase are enabled for all of flash program memory.
ps024315-1011 p r e l i m i n a r y operation z8 encore! xp ? f0823 series product specification 139 bits can only be set to 1. thus, sectors can be protected, but not unprotected, via register write operations. writing a value other than 5eh to the flash control register deselects the flash sector protect register and reen ables access to the page select register. observe the following procedure to setup th e flash sector protect register from user code: 1. write 00h to the flash control register to reset the flash controller. 2. write 5eh to the flash control register to select the flash sector protect register. 3. read and/or write the flash sector protect register which is now at register file address ff9h . 4. write 00h to the flash control register to return the flash controller to its reset state. ? the sector protect register is initialized to 0 on reset, putting each sector into an unpro- tected state. when a bit in the sector protec t register is written to 1, the corresponding sector can no longer be written or erased by the cpu. external flash programming through the ocd or via the flash controller by pass mode are unaffected. after a bit of the sector protect register has been set, it ca nnot be cleared except by powering down the device. byte programming the flash memory is enabled for byte progr amming after unlocking the flash controller and successfully enabling either mass erase or page erase. when the flash controller is unlocked and mass erase is successfully co mpleted, all program memory locations are available for byte programming. in contrast , when the flash controller is unlocked and page erase is successfully enabled, only the lo cations of the selected page are available for byte programming. an erased flash byte contains all 1?s ( ffh ). the programming opera- tion can only be used to change bits from 1 to 0. to change a flash bit (or multiple bits) from 0 to 1 requires execution of either the page erase or mass erase commands. byte programming is accomp lished using the on-chip debugger's write memory com- mand or ez8 cpu execution of the ldc or ldci instructions. for a description of the ldc and ldci instructions, refer to the ez8 cpu core user manual (um0128) , available for download at www.zilog.com . while the flash controller programs the flash memory, the ez8 cpu idles but the system clock and on -chip peripherals continue to operate. to exit programming mode and lock the flash, write any value to the flash control register, except the mass erase or page erase commands. the byte at each address of the flash memo ry cannot be programm ed (any bits written to 0) more than twice before an erase cycle occurs. doing so may r esult in corrupted data at the target byte. caution:
ps024315-1011 p r e l i m i n a r y operation z8 encore! xp ? f0823 series product specification 140 page erase the flash memory can be erased one page (512 bytes) at a time. page erasing the flash memory sets all bytes in that page to the value ffh . the flash page select register identi- fies the page to be erased. only a page resi ding in an unprotected sector can be erased. with the flash controller unlocked and the active page set, writing the value 95h to the flash control register initiates the page erase operation. while the flash controller exe- cutes the page erase operation, the ez8 cp u idles but the system clock and on-chip peripherals continue to operate. the ez8 cpu resumes operation after the page erase operation completes. if the page erase operation is performed using the on-chip debug- ger, poll the flash status register to determ ine when the page erase operation is complete. when the page erase is complete, the flash controller returns to its locked state. mass erase the flash memory can also be mass erased us ing the flash controller, but only by using the on-chip debugger. mass erasing the flas h memory sets all bytes to the value ffh . with the flash controller unlocked and the mass erase successfully enabled, writing the value 63h to the flash control register initiate s the mass erase operation. while the flash controller executes the mass erase oper ation, the ez8 cpu idles but the system clock and on-chip peripherals continue to operate. using the on-chip debugger, poll the flash status register to determine when th e mass erase operation is complete. when the mass erase is complete, the flash cont roller returns to its locked state. flash controller bypass the flash controller can be bypassed and the control signals for the flash memory brought out to the gpio pins. bypassing the flash controller allows faster row program- ming algorithms by controlling the flash programming signals directly. row programing is recommended for gang programming applications and large volume customers who do not require in-circuit initia l programming of the flash memory. page erase operations are also supported wh en the flash controller is bypassed. for more information about bypassing the flash controller, refer to the zilog application note titled, third-party flash programmin g support for z8 encore! mcus ( an0117) , available for download at www.zilog.com . flash controller behavior in debug mode the following changes in behavior of the fl ash controller occur when the flash control- ler is accessed using the on-chip debugger: ? the flash write protect option bit is ignored ? the flash sector protect register is ig nored for programming and erase operations
ps024315-1011 p r e l i m i n a r y flash control register definitions z8 encore! xp ? f0823 series product specification 141 ? programming operations are not limited to the page selected in the page select register ? bits in the flash sector protect register can be written to one or zero ? the second write of the page select regist er to unlock the flash controller is not necessary ? the page select register can be writte n when the flash controller is unlocked ? the mass erase command is enabled through the flash control register for security reasons, the flash controller allo ws only a single page to be opened for write/erase. when writing multiple flash pag es, the flash controller must repeat the un- lock sequence to select another page. flash control register definitions this section defines the features of the following flash control registers. f lash control register : see page 141 f lash status register : see page 143 f lash page select register : see page 143 f lash sector protect register : see page 145 f lash frequency high and low byte registers : see page 145 flash control register the flash controller must be unlocked usin g the flash control (ftctl) register before programming or erasing the fl ash memory. writing the sequence 73h 8ch , sequentially, to the flash control register unlocks the fl ash controller. when the flash controller is unlocked, the flash memory ca n be enabled for mass erase or page erase by writing the appropriate enable command to the fctl. pa ge erase applies only to the active page selected in flash page select register. mass erase is enabled only through the on-chip debugger. writing an invalid va lue or an invalid sequence returns the flash controller to its locked state. the write-only flash contro l register shares its register file address with the read-only flash status register. caution:
ps024315-1011 p r e l i m i n a r y flash control register definitions z8 encore! xp ? f0823 series product specification 142 table 81. flash control register (fctl) bit 7 6 5 4 3 2 1 0 field fcmd reset 00000000 r/w wwwwwwww address ff8h bit description [7:0] ? fcmd flash command 73h = first unlock command. 8ch = second unlock command. 95h = page erase command (must be third command in sequence to initiate page erase). 63h = mass erase command (must be third command in sequence to initiate mass erase). 5eh = enable flash sector protect register access.
ps024315-1011 p r e l i m i n a r y flash control register definitions z8 encore! xp ? f0823 series product specification 143 flash status register the flash status register indicates the current state of the flash controller. this register can be read at any time. the read-only flas h status register shares its register file address with the write-onl y flash control register. flash page select register the flash page select (fps) register shares address space with the flash sector protect register. unless the flash controller is unlocked and written with 5eh , writes to this address target the flash page select register. the register is used to select one of the ei ght available flash memory pages to be pro- grammed or erased. each flash page contains 512 bytes of flash memory. during a page erase operation, all flash memory having addr esses with the most significant 7-bits given by fps[6:0] are chosen for program/erase operation. table 82. flash status register (fstat) bit 7 6 5 4 3 2 1 0 field reserved fstat reset 00000000 r/w rrrrrrrr address ff8h bit description [7:6] reserved these bits are reserved and must be programmed to 0 when read. [5:0] ? fstat flash controller status 000000 = flash controller locked. 000001 = first unlock command received (73h written). 000010 = second unlock command received (8ch written). 000011 = flash controller unlocked. 000100 = sector protect register selected. 001xxx = program operation in progress. 010xxx = page erase operation in progress. 100xxx = mass erase operation in progress.
ps024315-1011 p r e l i m i n a r y flash control register definitions z8 encore! xp ? f0823 series product specification 144 table 83. flash page select register (fps) bit 7 6 5 4 3 2 1 0 field info_en page reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address ff9h bit description [7] ? info_en information area enable 0 = information area us not selected. 1 = information area is selected. the information area is mapped into the program memory address space at addresses fe00h through ffffh . [6:0] ? page page select this 7-bit field identifies the flash memory page for page erase and page unlocking. ? program memory address[15:9] = page[6:0]. ? for z8f04x3 devices, the upper 4 bits must always be 0. ? for z8f02x3 devices, the upper 5 bits must always be 0. ? for z8f01x3 devices, the upper 6 bits must always be 0.
ps024315-1011 p r e l i m i n a r y flash control register definitions z8 encore! xp ? f0823 series product specification 145 flash sector protect register the flash sector protect (fprot) register is shared with the flash page select register. when the flash control register is written with 5eh , the next write to this address targets the flash sector protect register. in all othe r cases, it targets the flash page select regis- ter. this register selects one of the 8 available flash memory sectors to be protected. the reset state of each sector protect bit is an unprotected state. after a sector is protected by setting its corresponding register bit, it cannot be un protected (the register bit cannot be cleared) without powering down the device. flash frequency high and low byte registers the flash frequency high (ffreqh) and lo w byte (ffreql) registers combine to form a 16-bit value, ffreq, to control tim ing for flash program and erase operations. the 16-bit binary flash frequency value must contain the system clock frequency (in khz) and is calculated us ing the following equation: table 84. flash sector protect register (fprot) bit 7 6 5 4 3 2 1 0 field sprot7 sprot6 sprot5 sprot4 sprot3 sprot2 sprot1 sprot0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address ff9h bit description [7] ? sprot n sector protection each bit corresponds to a 1024-byte flash sector on devices in the 8k range, while the remaining devices correspond to a 512-byte flash sector. to determine the appropriate flash memory sector address range and sector number for your Z8F0823 series product, please refer to table 79 on page 134 and to figure 20, which follows the table. ? for z8f08x3 and z8f04x3 devices, all bits are used. ? for z8f02x3 devices, the upper 4 bits are unused. ? for z8f01x3 devices, the upper 6 bits are unused. note: n indicates the specific flash sector (7?0). ffreq[15:0] ffreqh[ 7:0],ffreql[7:0] ?? system clock frequency 1000 ------------------------------------------------------------------ ==
ps024315-1011 p r e l i m i n a r y flash control register definitions z8 encore! xp ? f0823 series product specification 146 the flash frequency high and low byte regist ers must be loaded with the correct value to ensure proper operation of the device. al so, flash programming and erasure is not sup- ported for system clock frequencies below 20 khz or above 20 mhz. table 85. flash frequency high byte register (ffreqh) bit 7 6 5 4 3 2 1 0 field ffreqh reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address ffah bit description [7:0] ? ffreqh flash frequency high byte high byte of the 16-bit flash frequency value. table 86. flash frequency low byte register (ffreql) bit 7 6 5 4 3 2 1 0 field ffreql reset 0 r/w r/w address ffbh bit description [7:0] ? ffreql flash frequency low byte low byte of the 16-bit flash frequency value. caution:
ps024315-1011 p r e l i m i n a r y operation z8 encore! xp ? f0823 series product specification 147 option bit types this section describes the five types of fl ash option bits offered in the f083a series. user option bits the user option bits are contained in the first two bytes of program memory. access to these bits has been provided because these lo cations contain application-specific device configurations. the information contained here is lost when page 0 in program memory is erased. trim option bits the trim option bits are contained in a flash memory information page. these bits are fac- tory programmed values required to optimize the operation of onboard analog circuitry and cannot be permanently altered. program memory may be erased without endangering these values. it is possible to alter working values of these bits by accessing the trim bit address and data registers, but these workin g values are lost after a power loss or any other reset event. there are 32 bytes of trim data. to modify on e of these values the user code must first write a value between 00h and 1fh into the trim bit address register. the next write to the trim bit data register changes the working value of the target trim data byte. reading the trim data requires the u ser code to write a value between 00h and 1fh into the trim bit address register. the next read fro m the trim bit data register returns the working value of the target trim data byte. the trim address range is from information address 20?3f only. the remainder of the information page is not accessible through the trim bit address and data registers. calibration option bits the calibration option bits are also contained in the information page. these bits are fac- tory programmed values intende d for use in software correcting the device?s analog per- formance. to read these values, the user code must employ the ldc instruction to access the information area of the address space as defined in the flash information area section on page 15. serialization bits as an optional feature, zilog is able to provide factory-pr ogrammed serialization. for seri- alized products, the individual devices are pr ogrammed with unique serial numbers. these serial numbers are binary values, four bytes in length. the numbers increase in size with each device, but gaps in th e serial sequence may exist. note:
ps024315-1011 p r e l i m i n a r y flash option bit control register z8 encore! xp ? f0823 series product specification 148 these serial numbers are stored in the flash information page (for more details, see the reading the flash information page section on page 148 and the serialization data sec- tion on page 154) and are unaffected by mass erasure of the device?s flash memory. randomized lot identification bits as an optional feature, zilog is able to pr ovide a factory-programm ed random lot identi- fier. with this feature, all devices in a give n production lot are programmed with the same random number. this random number is uniquely regenerated for each successive produc- tion lot and is not like ly to be repeated. the randomized lot identifier is a 32-byte bina ry value, stored in the flash information page (for more details, see the reading the flash information page section on page 148 and the randomized lot identifier section on page 154) and is unaffected by mass erasure of the device?s flash memory. reading the flash information page the following code example shows how to r ead data from the flash information area. ? ; get value at info address 60 (fe60h) ? ldx fps, #%80 ; enable access to flash info page ? ld r0, #%fe ? ld r1, #%60 ? ldc r2, @rr0 ; r2 now contains the calibration value flash option bit control register definitions this section briefly describes the features of the trim bit address and data registers. trim bit address register the trim bit address (trmadr) register contai ns the target address for an access to the trim option bits. table 87. trim bit address register (trmadr) bit 7 6 5 4 3 2 1 0 field trmadr: trim bit address (00h to 1fh) reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address ff6h
ps024315-1011 p r e l i m i n a r y flash option bit address space z8 encore! xp ? f0823 series product specification 149 trim bit data register the trim bid data (trmdr) register contains th e read or write data for access to the trim option bits. flash option bit address space the first two bytes of flash program memory at addresses 0000h and 0001h are reserved for the user-programmable flash option bits. table 88. trim bit data register (trmdr) bit 7 6 5 4 3 2 1 0 field trmdr: trim bit data reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address ff7h table 89. flash option bits at program memory address 0000h bit 7 6 5 4 3 2 1 0 field wdt_res wdt_ao reserved vbo_ao frp reserved fwp reset u uuuuuuu r/w r/w r/w r/w r/w r/w r/w r/w r/w address program memory 0000h note: u = unchanged by reset. r/w = read/write. bit description [7] ? wdt_res watchdog timer reset 0 = watchdog timer time-out generates an inte rrupt request. in terrupts must be globally enabled for the ez8 cpu to acknowledge the interrupt request. 1 = watchdog timer time-out causes a system re set. this setting is the default for unpro- grammed (erased) flash. [6] ? wdt_ao watchdog timer always on 0 = watchdog timer is automatically enabled upon application of system power. watchdog timer can not be disabled. 1 = watchdog timer is enabled upon execution of the wdt instruction. once enabled, the watchdog timer can only be disabled by a reset or stop mode recovery. this setting is the default for unprogrammed (erased) flash. [5:4] reserved these bits are reserved and must be programmed to 11 during writes, and to 11 when read.
ps024315-1011 p r e l i m i n a r y flash option bit address space z8 encore! xp ? f0823 series product specification 150 [3] ? vbo_ao voltage brown-out protection always on 0 = voltage brown-out protection can be disabled in stop mode to reduce total power con- sumption. for the block to be disabled, the power control register bit must also be writ- ten (see the power control register 0 section on page 31). 1 = voltage brown-out protection is always enabled including during stop mode. this set- ting is the default for unprogrammed (erased) flash. [2] ? frp flash read protect 0 = user program code is inaccessible. limite d control features are available through the on-chip debugger. 1 = user program code is accessible. all on-chip debugger commands are enabled. this setting is the default for unprogrammed (erased) flash. [1] reserved this bit is reserved and must be programmed to 1. [0] ? fwp flash write protect this option bit provides fl ash program memory protection: 0 = programming and erasure disabled for all of flash program memory. programming, page erase, and mass erase through user c ode is disabled. mass erase is available using the on-chip debugger. 1 = programming, page erase, and mass erase are enabled for all of flash program mem- ory. table 90. flash options bits at program memory address 0001h bit 7 6 5 4 3 2 1 0 field reserved xtldis reserved reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w address program memory 0001h note: u = unchanged by reset. r/w = read/write. bit description (continued)
ps024315-1011 p r e l i m i n a r y trim bit address space z8 encore! xp ? f0823 series product specification 151 trim bit address space all available trim bit addresses and their func tions are listed in tables 91 through 93. bit description [7:5] reserved these bits are reserved and must be programmed to 111 during writes and to 111 when read. [4] ? xtldis state of crystal oscillator at reset this bit only enables the crystal oscillator. its selection as a system clock must be performed manually. 0 = the crystal oscillator is enabled during reset, resulting in lo nger reset timing. 1 = the crystal oscillator is disabled during reset, resulting in shorter reset timing. ? caution: programming the xtldis bit to zero on 8-pin versions of f0823 series devices pre- vents any further communication via the debug pin due to the x in and dbg functions being shared on pin 2 of the 8-pin package. do not pr ogram this bit to zero on 8-pin devices unless no further debugging or flash programming is required. [3:0] reserved these bits are reserved and must be programmed to 1111 during writes and to 1111 when read. table 91. trim options bits at address 0000h bit 7 6 5 4 3 2 1 0 field reserved reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w address information page memory 0020h note: u = unchanged by reset. r/w = read/write. bit description [7:0] reserved these bits are reserved. altering this regist er may result in incorrect device operation.
ps024315-1011 p r e l i m i n a r y zilog calibration data z8 encore! xp ? f0823 series product specification 152 zilog calibration data this section briefly describes the features of the following flash option bit calibration registers. adc calibration data : see page 153 serialization data : see page 154 randomized lot identifier : see page 154 table 92. trim option bits at 0001h bit 7 6 5 4 3 2 1 0 field reserved reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w address information page memory 0021h note: u = unchanged by reset. r/w = read/write. bit description [7:0] reserved these bits are reserved. altering this regist er may result in incorrect device operation. table 93. trim option bits at 0002h (tipo) bit 7 6 5 4 3 2 1 0 field ipo_trim reset u r/w r/w address information page memory 0022h note: u = unchanged by reset. r/w = read/write. bit description [7:0] ? ipo_trim internal precision oscillator trim byte contains trimming bits for th e internal precision oscillator.
ps024315-1011 p r e l i m i n a r y zilog calibration data z8 encore! xp ? f0823 series product specification 153 adc calibration data table 94. adc calibration bits bit 7 6 5 4 3 2 1 0 field adc_cal reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w address information page memory 0060h?007dh note: u = unchanged by reset. r/w = read/write. bit description [7:0] ? adc_cal analog-to-digital converter calibration values contains factory-calibrated values for adc gain and offset compensation. each of the ten supported modes has one byte of offset calibration and two bytes of gain calibration. these values are read by the software to compensate adc measurements as detailed in the soft- ware compensation procedure section on page 126. the location of each calibration byte is provided in table 95. table 95. adc calibration data location info page address memory address compensation usage adc mode reference type 60 fe60 offset single-ended unbuffered internal 2.0 v 08 fe08 gain high byte single-ended unbuffered internal 2.0 v 09 fe09 gain low byte single-ended unbuffered internal 2.0 v 63 fe63 offset single-ended unbuffered internal 1.0 v 0a fe0a gain high byte single-ended unbuffered internal 1.0 v 0b fe0b gain low byte single-ended unbuffered internal 1.0 v 66 fe66 offset single-ended unbuffered external 2.0 v 0c fe0c gain high byte single-ended unbuffered external 2.0 v 0d fe0d gain low byte single-ended unbuffered external 2.0 v
ps024315-1011 p r e l i m i n a r y zilog calibration data z8 encore! xp ? f0823 series product specification 154 serialization data randomized lot identifier table 96. serial number at 001c?001f (s_num) bit 7 6 5 4 3 2 1 0 field s_num reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w address information page memory 001c?001f note: u = unchanged by reset. r/w = read/write. bit description [7:0] ? s_num serial number byte the serial number is a unique four -byte binary value; see table 97. table 97. serialization data locations info page address memory address usage 1c fe1c serial number byte 3 (most significant). 1d fe1d serial number byte 2. 1e fe1e serial number byte 1. 1f fe1f serial number byte 0 (least significant). table 98. lot identification number (rand_lot) bit 7 6 5 4 3 2 1 0 field rand_lot reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w address interspersed throughout information page memory note: u = unchanged by reset. r/w = read/write. bit description [7] ? rand_lot randomized lot id the randomized lot id is a 32-byte binary value that changes for each production lot; see table 99.
ps024315-1011 p r e l i m i n a r y zilog calibration data z8 encore! xp ? f0823 series product specification 155 table 99. randomized lot id locations info page address memory address usage 3c fe3c randomized lot id byte 31 (most significant) 3d fe3d randomized lot id byte 30 3e fe3e randomized lot id byte 29 3f fe3f randomized lot id byte 28 58 fe58 randomized lot id byte 27 59 fe59 randomized lot id byte 26 5a fe5a randomized lot id byte 25 5b fe5b randomized lot id byte 24 5c fe5c randomized lot id byte 23 5d fe5d randomized lot id byte 22 5e fe5e randomized lot id byte 21 5f fe5f randomized lot id byte 20 61 fe61 randomized lot id byte 19 62 fe62 randomized lot id byte 18 64 fe64 randomized lot id byte 17 65 fe65 randomized lot id byte 16 67 fe67 randomized lot id byte 15 68 fe68 randomized lot id byte 14 6a fe6a randomized lot id byte 13 6b fe6b randomized lot id byte 12 6d fe6d randomized lot id byte 11 6e fe6e randomized lot id byte 10 70 fe70 randomized lot id byte 9 71 fe71 randomized lot id byte 8 73 fe73 randomized lot id byte 7 74 fe74 randomized lot id byte 6 76 fe76 randomized lot id byte 5 77 fe77 randomized lot id byte 4 79 fe79 randomized lot id byte 3 7a fe7a randomized lot id byte 2 7c fe7c randomized lot id byte 1 7d fe7d randomized lot id byte 0 (least significant)
ps024315-1011 p r e l i m i n a r y on-chip debugger z8 encore! xp ? f0823 series product specification 156 on-chip debugger z8 encore! xp f0823 series devices contai n an integrated on-chip debugger (ocd) which provides advanced debu gging features that include: ? single pin interface ? reading and writing of the register file ? reading and writing of program and data memory ? setting of breakpoints and watchpoints ? executing ez8 cpu instructions ? debug pin sharing with general-purpose input-output function to maximize the pins available architecture the on-chip debugger consists of four primar y functional blocks: tr ansmitter, receiver, auto-baud detector/generator, an d debug controller. figure 22 displays the architecture of the ocd. figure 22. on-chip debugger block diagram auto-baud system clock transmitter receiver dbg pin debug controller ez8 cpu control detector/generator
ps024315-1011 p r e l i m i n a r y operation z8 encore! xp ? f0823 series product specification 157 operation the following section describ es the operation of the ocd. ocd interface the ocd uses the dbg pin for communication w ith an external host. this one-pin inter- face is a bidirectional open-drain interface that transmits and receives data. data transmis- sion is half-duplex, in that transmit and receive cannot oc cur simultaneously. the serial data on the dbg pin is sent using the standard asynchronous data format defined in rs- 232. this pin creates an interface from the f08 23 series products to the serial port of a host pc using minimal external hardware.t wo different methods for connecting the dbg pin to an rs-232 interface are displayed in figure 23 and figure 24. the recommended method is the buffered implem entation depicted in figure 24. the dbg pin has a internal pull-up resistor which is sufficient for some applications (for more details about the pull- up current, see the electrical characteristics chapter on page 196). for ocd operation at higher data rates or in noisy systems, zilo g recommends an external pull-up resistor. for operation of the ocd, all power pins (v dd and av dd ) must be supplied with power, and all ground pins (v ss and av ss ) must be properly grounded. the dbg pin is open- drain and may require an external pull-up resistor to ensure proper operation. figure 23. interfacing the on-chip debugger?s dbg pin with an rs-232 interface, # 1 of 2 caution: rs-232 tx rs-232 rx rs-232 transceiver vdd dbg pin 10 k ? schottky diode
ps024315-1011 p r e l i m i n a r y operation z8 encore! xp ? f0823 series product specification 158 debug mode the operating characteristics of the devices in debug mode are: ? the ez8 cpu fetch unit stops, idling the ez8 cpu, unless directed by the ocd to ex- ecute specific instructions ? the system clock operates unless in stop mode ? all enabled on-chip peripherals operate unless in stop mode ? automatically exits halt mode ? constantly refreshes the wa tchdog timer, if enabled. entering debug mode the device enters debug mode fo llowing the operations below: ? the device enters debug mode after the ez8 cpu executes a brk (breakpoint) in- struction ? if the dbg pin is held low during the most re cent clock cycle of system reset, the part enters debug mode up on exiting system reset holding the dbg pin low for an additional 5000 (minimum) cloc k cycles after reset (making sure to account for any specified frequ ency error if using an internal oscillator) prevents a false interpretation of an autobaud sequence (see the ocd autobaud detector/ generator section on page 159 ). figure 24. interfacing the on-chip debugger?s dbg pin with an rs-232 interface, # 2 of 2 rs-232 tx rs-232 rx rs-232 transceiver vdd dbg pin 10 k ? open-drain buffer note:
ps024315-1011 p r e l i m i n a r y operation z8 encore! xp ? f0823 series product specification 159 ? if the pa2/reset pin is held low while a 32-bit ke y sequence is issued to the pa0/ dbg pin, the dbg feature is unlocked. after releasing pa2/reset , it is pulled high. at this point, the pa0/dbg pin can be used to autobaud and cause the device to enter ? debug mode. for more details, see the ocd unlock sequence (8-pin devices only) section on page 161. exiting debug mode the device exits debug mode foll owing any of these operations: ? clearing the dbgmode bit in th e ocd control register to 0 ? power-on reset ? voltage brown-out reset ? watchdog timer reset ? asserting the reset pin low to initiate a reset ? driving the dbg pin low while the device is in stop mode initia tes a system reset ocd data format the ocd interface uses the asynchronous data format defined for rs-232. each character is transmitted as 1 start bit, 8 data bits (least -significant bit first), and 1 stop bit as dis- played in figure 25. when responding to a request for data, the ocd may comm ence transmitting immediately after receiving the stop bit of an incoming fra me. therefore, when se nding the stop bit, the host must not actively drive the dbg pin high for more than 0.5 bit times. zilog recom- mends that, if possible, the host drives the dbg pin using an open-drain output. ocd autobaud detector/generator to run over a range of baud rates (data bits per second) with various system clock frequen- cies, the ocd contains an auto-baud detector /generator. after a reset, the ocd is idle until it receives data. the ocd requires that th e first character sent from the host is the character 80h . the character 80h has eight continuous bits low (one start bit plus 7 data figure 25. ocd data format startd0d1d2d3d4d5d6d7stop note:
ps024315-1011 p r e l i m i n a r y operation z8 encore! xp ? f0823 series product specification 160 bits), framed between high bits. the auto-baud detector measures this period and sets the ocd baud rate generator accordingly. the auto-baud detector/generator is clocked by the system clock. the minimum baud rate is the system clock frequency divided by 51 2. for optimal operation with asynchronous datastreams, the maximum recommended baud ra te is the system clock frequency divided by eight. the maximum possible baud rate fo r asynchronous datastreams is the system clock frequency divided by four, but this theoretical maximum is possible only for low noise designs with clean signals. table 100 lists minimum and recommended maximum baud rates for sample crystal frequencies. if the ocd receives a serial break (nine or more continuous bits low) the auto-baud detector/generator resets. re configure the auto-baud det ector/generator by sending 80h . ocd serial errors the ocd detects any of the followin g error conditions on the dbg pin: ? serial break (a minimum of nine continuous bits low) ? framing error (received stop bit is low) ? transmit collision (ocd and ho st simultaneous transmissi on detected by the ocd) ? when the ocd detects one of these errors, it aborts any command currently in progress, transmits a four character long serial brea k back to the host, and resets the auto-baud detector/generator. a framing error or transmit collision may be caused by the host sending a serial break to the ocd. because of the open-drain natu re of the interface, returning a serial break break back to the host only extends the length of the serial break if the host releases the serial break early. the host transmits a serial break on the dbg pin when first connecting to the f0823 series devices or when recovering from an error. a serial break from the host resets the auto- baud generator/detector but does not reset the ocd control register. a serial break leaves the device in debug mode if that is the current mode. the ocd is held in reset until the end of the serial br eak when the dbg pin returns high. because of the open- drain nature of the dbg pin, the host sends a serial break to the ocd even if the ocd is transmitting a character. table 100. ocd baud-rate limits system clock frequency (mhz) recommended maximum baud rate (kbps) recommended standard pc baud rate (bps) minimum baud rate (kbps) 5.5296 1382.4 691,200 1.08 0.032768 (32 khz) 4.096 2400 0.064
ps024315-1011 p r e l i m i n a r y operation z8 encore! xp ? f0823 series product specification 161 ocd unlock sequence (8-pin devices only) because of pin-sharing on the 8-pin device, an unlock sequence must be performed to access the dbg pin. if this sequence is not completed during a system reset, then the pa0/ dbg pin functions only as a gpio pin. the following sequence unlocks the dbg pin: 1. hold pa2/reset low. 2. wait 5 ms for the internal reset sequence to complete. 3. send the following bytes serially to the debug pin: dbg 80h (autobaud) dbg ebh dbg 5ah dbg 70h dbg cdh (32-bit unlock key) 4. release pa2/reset . the pa0/dbg pin is now identical in function to that of the dbg pin on the 20- or 28-pin device. to enter debug mode, reautobaud and write 80h to the ocd control register (see the on-chip debugger commands section on page 162). breakpoints execution breakpoints ar e generated using the brk instruction (opcode 00h ). when the ez8 cpu decodes a brk instruction, it signals the ocd. if breakpoints are enabled, the ocd enters debug mode and idles the ez8 cpu. if breakpoints are not enabled, the ocd ignores the brk signal and the brk instruction operates as an nop instruction. breakpoints in flash memory the brk instruction is opcode 00h , which corresponds to the fu lly programmed state of a byte in flash memory. to implement a breakpoint, write 00h to the required break address, overwriting the current instruction. to remove a breakpoi nt, the corresponding page of flash memory must be erased an d reprogrammed with the original data. runtime counter the ocd contains a 16-bit runtime counter . it counts system clock cycles between breakpoints. the counter starts counting when the ocd leaves debug mode and stops counting when it enters debug mode again or when it reaches th e maximum count of ffffh .
ps024315-1011 p r e l i m i n a r y on-chip debugger commands z8 encore! xp ? f0823 series product specification 162 on-chip debugger commands the host communicates to th e ocd by sending ocd commands using the dbg interface. during normal operation, only a subset of the ocd commands are available. in debug mode, all ocd commands become available unl ess the user code and control registers are protected by programming the flash read protect option bit ( frp ). the flash read pro- tect option bit prevents the code in memory from being read out of z8 encore! xp f0823 series products. when this option is enabled, several of the ocd co mmands are disabled. table 101 is a summary of the ocd commands. each ocd command is described in fur- ther detail in the pages that follow this table. table 102 on page 167 also indicates those commands that operate when the device is not in debug mode (normal operation) and those commands that are disabled by prog ramming the flash read protect option bit. table 101. ocd commands debug command command byte enabled when not in debug mode? disabled by flash read protect option bit read ocd revision 00h yes ? reserved 01h ? ? read ocd status register 02h yes ? read runtime counter 03h ? ? write ocd control register 04h yes cannot clear dbgmode bit. read ocd control register 05h yes ? write program counter 06h ? disabled. read program counter 07h ? disabled. write register 08h ? only writes of the flash memory con- trol registers are allowed. additionally, only the mass erase command is allowed to be written to the flash con- trol register. read register 09h ? disabled. write program memory 0ah ? disabled. read program memory 0bh ? disabled. write data memory 0ch ? yes. read data memory 0dh ? ? read program memory crc 0eh ? ? reserved 0fh ? ? step instruction 10h ? disabled. stuff instruction 11h ? disabled. execute instruction 12h ? disabled. reserved 13h?ffh ? ?
ps024315-1011 p r e l i m i n a r y on-chip debugger commands z8 encore! xp ? f0823 series product specification 163 in the following list of ocd commands, data and commands sent from the host to the ocd are identified by ?dbg command/data? . data sent from the ocd back to the host is identified by ?dbg data? . read ocd revision (00h). the read ocd revision comman d determines the version of the ocd. if ocd commands are added, remo ved, or changed, this revision number changes. dbg 00h dbg ocdrev[15:8] (major revision number) dbg ocdrev[7:0] (minor revision number) read ocd status register (02h). the read ocd status register command reads the ocdstat register. dbg 02h dbg ocdstat[7:0] read runtime counter (03h). the runtime counter counts system clock cycles in between breakpoints. th e 16-bit runtime counter counts up from 0000h and stops at the maximum count of ffffh . the runtime counter is overwritten during the write memory, read memory, write register, read register, read memory crc, step instruction, stuff instruction, and execut e instruction commands. dbg 03h dbg runtimecounter[15:8] dbg runtimecounter[7:0] write ocd control register (04h). the write ocd control register command writes the data that follows to the ocdctl register . when the flash read protect option bit is enabled, the dbgmode bit ( ocdctl [7]) can only be set to 1, it cannot be cleared to 0 and the only method of returning the device to normal operating mode is to reset the device. dbg 04h dbg ocdctl[7:0] read ocd control register (05h). the read ocd control regi ster command reads the value of the ocdctl register. dbg 05h dbg ocdctl[7:0] write program counter (06h). the write program counter command writes the data that follows to the ez8 cpu?s program coun ter (pc). if the device is not in debug mode or if the flash read protect option bit is enabled, the progra m counter (pc) values are discarded. dbg 06h dbg programcounter[15:8] dbg programcounter[7:0]
ps024315-1011 p r e l i m i n a r y on-chip debugger commands z8 encore! xp ? f0823 series product specification 164 read program counter (07h). the read program counter co mmand reads the value in the ez8 cpu?s program counter (pc). if the device is not in debug mode or if the flash read protect option bit is en abled, this command returns ffffh . dbg 07h dbg programcounter[15:8] dbg programcounter[7:0] write register (08h). the write register command writes data to the register file. data can be written 1?256 bytes at a time (256 bytes can be written by setting size to 0). if the device is not in debug mode, the address and data values are discarded. if the flash read protect option bit is enabled, only writes to the flash control registers are allowed and all other register write data values are discarded. dbg 08h dbg {4?h0,register address[11:8]} dbg register address[7:0] dbg size[7:0] dbg 1?256 data bytes read register (09h). the read register command reads data from the register file. data can be read 1?256 bytes at a time (256 bytes can be read by setting size to 0). if the device is not in debug mode or if the flash read protect op tion bit is enabled, this com- mand returns ffh for all the data values. dbg 09h dbg {4?h0,register address[11:8] dbg register address[7:0] dbg size[7:0] dbg 1?256 data bytes write program me mory (0ah). the write program memory command writes data to program memory. this command is equivalent to the ldc and ldci instructions. data can be written 1?65536 bytes at a time (65536 bytes can be written by setting size to 0). the on-chip flash controller must be written to and unlocked for the programming operation to occur. if the flash controller is not unlocked, the data is discarded. if the device is not in debug mode or if the flash read protect option bit is enabled, the data is discarded. dbg 0ah dbg program memory address[15:8] dbg program memory address[7:0] dbg size[15:8] dbg size[7:0] dbg 1?65536 data bytes read program memory (0bh). the read program memory command reads data from program memory. this command is equivalent to the ldc and ldci instructions. data can be read 1?65536 bytes at a time (65536 bytes can be read by setting size to 0). if the device is not in debug mode or if the flas h read protect option bit is enabled, this command returns ffh for the data.
ps024315-1011 p r e l i m i n a r y on-chip debugger commands z8 encore! xp ? f0823 series product specification 165 dbg 0bh dbg program memory address[15:8] dbg program memory address[7:0] dbg size[15:8] dbg size[7:0] dbg 1?65536 data bytes write data memory (0ch). the write data memory comman d writes data to data mem- ory. this command is equivalent to the lde and ldei instructions. data can be written 1? 65536 bytes at a time (65536 bytes can be writte n by setting size to 0). if the device is not in debug mode or if the flash read protect option bit is enabled, the data is discarded. dbg 0ch dbg data memory address[15:8] dbg data memory address[7:0] dbg size[15:8] dbg size[7:0] dbg 1?65536 data bytes read data memory (0dh). the read data memory comm and reads from data memory. this command is e quivalent to the lde and ldei instructions. data can be read 1 to 65536 bytes at a time (65536 bytes can be read by setting size to 0). if the device is not in debug mode, this command returns ffh for the data. dbg 0dh dbg data memory address[15:8] dbg data memory address[7:0] dbg size[15:8] dbg size[7:0] dbg 1?65536 data bytes read program memory crc (0eh). the read program memory cyclic redundancy check (crc) command co mputes and returns the crc of program memory using the 16- bit crc-ccitt polynomial. if the device is no t in debug mode, this command returns ffffh for the crc value. unlike most other oc d read commands, there is a delay from issuing of the command until the ocd returns the data. the ocd reads the program memory, calculates the crc value, and returns the result. the delay is a function of the program memory size and is approximately equa l to the system clock period multiplied by the number of bytes in the program memory. dbg 0eh dbg crc[15:8] dbg crc[7:0] step instruction (10h). the step instruction steps one as sembly instruction at the current program counter (pc) location. if the device is not in debug mode or the flash read protect option bit is enabled, the ocd ignores this command. dbg 10h
ps024315-1011 p r e l i m i n a r y on-chip debugger control register z8 encore! xp ? f0823 series product specification 166 stuff instruction (11h). the stuff command steps one assembly instruction and allows specification of the first byte of the instructio n. the remaining 0?4 bytes of the instruction are read from program memory. this command is useful for stepping over instructions where the first byte of the instruction has been overwritten by a breakpoint. if the device is not in debug mode or the flash read pr otect option bit is enab led, the ocd ignores this command. dbg 11h dbg opcode[7:0] execute instruction (12h). the execute command a llows sending an entire instruction to be executed to the ez8 cpu. this command can also step over breakpoints. the number of bytes to send for the instruction depends on the opcode. if the device is not in debug mode or the flash read protect option bit is enabled, this command reads and discards one byte. dbg 12h dbg 1?5 byte opcode on-chip debugger control register definitions this section describes the features of the on -chip debugger control and status registers. ocd control register the ocd control register controls the state of the ocd. this register is used to enter or exit debug mode and to enable the brk instruction. it also r esets z8 encore! xp f0823 series device. a reset and stop function can be achieved by writing 81h to this register. a reset and go function can be achieved by writing 41h to this register. if the device is in debug mode, a run function can be implemented by writing 40h to this register.
ps024315-1011 p r e l i m i n a r y on-chip debugger control register z8 encore! xp ? f0823 series product specification 167 table 102. ocd contro l register (ocdctl) bit 7 6 5 4 3 2 1 0 field dbgmode brken dbgack reserved rst reset 0 0000000 r/w r/wr/wr/wrrrrr/w bit description [7] ? dbgmode debug mode the device enters debug mode when this bi t is 1. when in debug mode, the ez8 cpu stops fetching new instructions. clearing this bit causes the ez8 cpu to restart. this bit is automatically set when a brk instruction is decoded and breakpoints are enabled. if the flash read protect option bit is enabled, this bit can only be cleared by resetting the device. it cannot be written to 0. 0 = f0823 series device is operating in normal mode. 1 = f0823 series device is in debug mode. [6] ? brken breakpoint enable this bit controls the behavior of the brk instruction (opcode 00h ). by default, breakpoints are disabled and the brk instruction behaves similar to an nop instruction. if this bit is 1, when a brk instruction is decoded, the dbgmode bit of the ocdctl register is automati- cally set to 1. 0 = breakpoints are disabled. 1 = breakpoints are enabled. [5] ? dbgack debug acknowledge this bit enables the debug acknowledge feature. if this bit is set to 1, the ocd sends a debug acknowledge character ( ffh ) to the host when a breakpoint occurs. 0 = debug acknowledge is disabled. 1 = debug acknowledge is enabled. [4:1] reserved these bits are reserved and must be 00000 when read. [0] ? rst reset setting this bit to 1 resets the z8f04xa family device. the device goes through a normal power-on reset sequence with the exception that the ocd is not reset. this bit is automat- ically cleared to 0 at the end of reset. 0 = no effect. 1 = reset the flash read protect option bit device.
ps024315-1011 p r e l i m i n a r y on-chip debugger control register z8 encore! xp ? f0823 series product specification 168 ocd status register the ocd status register reports status inform ation about the current state of the debugger and the system. table 103. ocd status register (ocdstat) bit 7 6 5 4 3 2 1 0 field dbg halt frpenb reserved reset 00000000 r/w rrrrrrrr bit description [7] ? dbg debug status 0 = normal mode. 1 = debug mode. [6] ? halt halt mode 0 = not in halt mode. 1 = in halt mode. [5] ? frpenb flash read protect option bit enable 0 = frp bit enabled to allow disabling of many ocd commands. 1 = frp bit has no effect. [4:0] reserved these bits are reserved and must be 00000 when read.
ps024315-1011 p r e l i m i n a r y oscillator control z8 encore! xp ? f0823 series product specification 169 oscillator control z8 encore! xp f0823 series devices uses th ree possible clocking schemes, each user- selectable. these three schemes are: ? on-chip precision trimmed rc oscillator ? external clock drive ? on-chip low power watchdog timer oscillator ? in addition, f0823 series devices contain cloc k failure detection and recovery circuitry, which allow continued oper ation despite a failure of the primary oscillator. operation this chapter discusses the logic used to select the system clock and handle primary oscil- lator failures. a description of the specific op eration of each oscill ator is outlined else- where in this document. system clock selection the oscillator control block selects from the av ailable clocks. table 104 details each clock source and its usage. table 104. oscillator conf iguration and selection clock source characteristics required setup internal precision rc oscillator ? 32.8 khz or 5.53 mhz ? 4% accuracy when trimmed ? no external components required ? unlock and write oscillator control register (oscctl) to enable and select oscillator at either 5.53 mhz or ? 32.8 khz external clock drive ? 0 to 20 mhz ? accuracy dependent on external clock source ? write gpio registers to configure pb3 pin for external clock function ? unlock and write oscctl to select external system clock ? apply external clock signal to gpio internal watchdog timer oscillator ? 10 khz nominal ? 40% accuracy; no external compo- nents required ? very low power consumption ? enable wdt if not enabled and wait until wdt oscillator is operating. ? unlock and write oscillator control register (oscctl) to enable and select oscillator
ps024315-1011 p r e l i m i n a r y operation z8 encore! xp ? f0823 series product specification 170 unintentional accesses to the o scillator control register can actually stop the chip by switching to a non-functioning oscillator. to prevent this co ndition, the oscillator control block employs a register unlocking/locking scheme. osc control register unlocking/locking to write to the oscillator control register, unlock it by making two writes to the osc- ctl register with the values e7h followed by 18h . a third write to the oscctl regis- ter changes the value of the actual register a nd returns the register to a locked state. any other sequence of oscillator control register writes has no effect. the values written to unlock the register must be ordered correctly, but are not necessarily co nsecutive. it is pos- sible to write to or read from other regist ers within the unlock ing/locking operation. when selecting a new clock source, the primary oscillator failure detection circuitry and the watchdog timer oscillator failure circu itry must be disabled. if pofen and wofen are not disabled prior to a clock switch-over, it is possible to generate an interrupt for a failure of either oscillator. the failure dete ction circuitry can be enabled anytime after a successful write of oscsel in th e oscillator control register. the internal precision oscillator is enabled by default. if the user code changes to a differ- ent oscillator, it is appropriate to disable the ipo for power savings. disabling the ipo does not occur automatically. clock failure detection and recovery should an oscillator or timer fail, there ar e methods of recovery, as this section describes. primary oscillator failure z8 encore! xp f0823 series devices can gene rate non-maskable interrupt-like events when the primary oscillator fails. to maintain system function in this situation, the clock failure recovery circuitry auto matically forces the watchdog timer oscillator to drive the system clock. the watchdog timer oscillator must be enabled to allow the recovery. although this oscillator runs at a much slower speed than th e original system clock, the cpu continues to operate, allo wing execution of a clock failure vector and software rou- tines that either remedy the oscillator failure or issue a failure alert. this automatic switch- over is not available if the watchdog timer is the primary oscillator. it is also unavailable if the watchdog timer oscillator is disabled , though it is not necessary to enable the watchdog timer reset func tion outlined in the the watchdog timer section on page 91. the primary oscillator failure detection circuitry asserts if the system clock frequency drops below 1 khz 50%. if an external signal is selected as the system oscillator, it is pos- sible that a very slow but no n-failing clock can generate a failure condition. under these caution:
ps024315-1011 p r e l i m i n a r y oscillator control register definitions z8 encore! xp ? f0823 series product specification 171 conditions, do not enable the cl ock failure circuitry (pofen must be deasserted in the oscctl register). watchdog timer failure in the event of a watchdog timer oscillator failure, a similar non-maskable interrupt-like event is issued. this event does not trigger an attendant clock switch-over, but alerts the cpu of the failure. after a watchdog timer failu re, it is no longer possible to detect a pri- mary oscillator failure. the failure detection circuitry does not function if the watchdog timer is used as the primary oscillator or if the watchdog timer oscillator has been dis- abled. for either of these cases, it is necessar y to disable the detection circuitry by deas- serting the wdfen bit of the oscctl register. the watchdog timer oscillator failure detec tion circuit counts system clocks while searching for a watchdog timer clock. the logi c counts 8004 system clock cycles before determining that a failure has occurred. the system clock rate determines the speed at which the watchdog timer failur e can be detected. a very slow system clock results in very slow detection times. it is possible to disable the clock failure detection circuitry as well as all functioning clock sources. in this case, the z8 encore! xp f0823 series device ceases functioning and can only be recovered by power-on reset. oscillator control register definitions the following section provides the bit definitions for the oscillator control register. oscillator control register the oscillator control register (oscctl) enables/disables the various oscillator circuits, enables/disables the failure detection/recovery circuitry and selects the primary oscillator, which becomes th e system clock. the oscillator control register must be un locked before writing. writing the two step sequence e7h followed by 18h to the oscillator control regi ster unlocks it. the register is locked at successful completion of a register write to the oscctl. caution:
ps024315-1011 p r e l i m i n a r y oscillator control register definitions z8 encore! xp ? f0823 series product specification 172 table 105. oscillator control register (oscctl) bit 7 6 5 4 3 2 1 0 field inten reserved wdten pofen wdfen scksel reset 10100000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f86h bit description [7] ? inten internal precision oscillator enable 1 = internal precision oscillator is enabled. 0 = internal precision oscillator is disabled. [6] reserved this bit is reserved and must be programmed to 0 during writes and to 0 when read. [5] ? wdten watchdog timer oscillator enable 1 = watchdog timer oscillator is enabled. 0 = watchdog timer os cillator is disabled. [4] ? pofen primary oscillator failure detection enable 1 = failure detection and recovery of primary oscilla tor is enabled. 0 = failure detection and recovery of primary oscilla tor is disabled. [3] ? wdfen watchdog timer oscillator failure detection enable 1 = failure detection of watchd og timer oscillator is enabled. 0 = failure detection of watchdog timer oscillator is disabled. [2:0] ? scksel system clock oscillator select 000 = internal precision oscillator func tions as system clock at 5.53 mhz. 001 = internal precision oscillator f unctions as system clock at 32 khz. 010 = reserved. 011 = watchdog timer oscillato r functions as system clock. 100 = external clock signal on pb3 functions as system clock. 101 = reserved. 110 = reserved. 111 = reserved.
ps024315-1011 p r e l i m i n a r y int ernal precision oscillator z8 encore! xp ? f0823 series product specification 173 internal precision oscillator the internal precision oscillator (ipo) is de signed for use without external components. you can either manually trim the oscillator for a non-standard frequency or use the auto- matic factory-trimmed version to achieve a 5.53 mhz frequency. the features of ipo include: ? on-chip rc oscillator that does not require external components ? output frequency of either 5.53 mhz or 32.8 khz (contains both a fast and a slow mode) ? trimming possible through flash option bits with user override ? elimination of crystals or ceramic resonato rs in applications where high timing accu- racy is not required operation an 8-bit trimming register, incorporated into the design, compensates for absolute varia- tion of oscillator frequency. once trimmed the o scillator frequency is stable and does not require subsequent calibration. trimming is performed during manufacturing and is not necessary for you to repeat unless a frequen cy other than 5.53 mhz (fast mode) or 32.8 khz (slow mode) is required. this trimming is done at +30c and a supply voltage of 3.3 v, so accuracy of this operating point is optimal. power down this block for minimum system powe r. by default, the o scillator is configured through the flash option bits. however, the us er code can override these trim values, as described in the trim bit address space section on page 151. select one of the two frequencies for the oscillator: 5.53 mhz and 32.8 khz, using the oscsel bits in the oscillator control chapter on page 169.
ps024315-1011 p r e l i m i n a r y ez8 cpu instruction set z8 encore! xp ? f0823 series product specification 174 ez8 cpu instruction set this chapter describes the following feat ures of the ez8 cpu instruction set: assembly language programming introduction : see page 174 assembly language syntax : see page 175 ez8 cpu instruction notation : see page 176 ez8 cpu instruction classes : see page 178 ez8 cpu instruction summary : see page 182 assembly language programming introduction the ez8 cpu assembly language provides a me ans for writing an application program without concern for actual memory addresses or machine instruction formats. a program written in assembly language is called a sour ce program. assembly language allows the use of symbolic addresses to identify memory locations. it also allows mnemonic codes (opcodes and operands) to represent the inst ructions themselves. th e opcodes identify the instruction while the operands represent memory locations, registers, or immediate data values. each assembly language program consists of a series of symbolic commands called state- ments . each statement can contain labels, operations, operands, and comments. labels are assigned to a particular instructio n step in a source program. the label identi- fies that step in the program as an en try point for use by other instructions. the assembly language also includes assembl er directives that supplement the machine instruction. the assembler directives, or p seudo-ops, are not transl ated into a machine instruction. rather, the pseudo-ops are interp reted as directives that control or assist the assembly process. the source program is processed (assembled) by the assembler to obtain a machine lan- guage program called the object code. the object code is executed by the ez8 cpu. an example segment of an assembly language pr ogram is detailed in the following example.
ps024315-1011 p r e l i m i n a r y assembly language syntax z8 encore! xp ? f0823 series product specification 175 assembly language s ource program example assembly language syntax for proper instruction execution, ez8 cpu ass embly language syntax requires that the operands be written as ?destination, source?. after assembly, the obj ect code usually has the operands in the order ?source, destination?, but ordering is opcode-dependent. the ? following instruction ex amples illustrate the format of some basic assembly instructions and the resulting object code produced by th e assembler. you must follow this binary for- mat if you prefer manual program coding or intend to implement your own assembler. example 1 if the contents of registers 43h and 08h are added and the result is stored in 43h , the assembly syntax and resulting object code is shown in table 106. example 2 in general, when an instructio n format requires an 8-bit register address, that address can specify any register location in the range 0?255 or, using escaped mode addressing, a working register r0?r15. if the contents of register 43h and working register r8 are added and the result is stored in 43h , the assembly syntax and resulting object code is shown in table 107. jp start ; everything after the semicolon is a comment. start: ; a label called ?start?. the first instruction ( jp start ) in this ; example causes program execution to jump to the point within the ; program where the start label occurs. ld r4, r7 ; a load (ld) instruction with two operands. the first operand, ; working register r4, is the destination. the second operand, ; working register r7, is the so urce. the contents of r7 is ; written into r4. ld 234h, #%01 ; another load (ld) instruction with two operands. ; the first operand, extend ed mode register address 234h , ; identifies the destination. the second operand, immediate data ; value 01h , is the source. the value 01h is written into the ; register at address 234h. table 106. assembly language syntax example 1 assembly language code add 43h, 08h (add dst, src) object code 04 08 43 (opc src, dst)
ps024315-1011 p r e l i m i n a r y ez8 cpu instruction notation z8 encore! xp ? f0823 series product specification 176 see the device-specific z8 encore! xp produc t specification to determine the exact regis- ter file range available. the register file size varies, depending on the device type. ez8 cpu instruction notation in the ez8 cpu instruction summary and description sections, the operands, condition codes, status flags, and addr ess modes are represented by a notational shorthand that is noted in table 108 . table 107. assembly language syntax example 2 assembly language code add 43h, r8 (add dst, src) object code 04 e8 43 (opc src, dst) table 108. notational shorthand notation description operand range b bit b b represents a value from 0 to 7 (000b to 111b). cc condition code ? see the condition codes overview in the ez8 cpu core user manual (um0128) . da direct address addrs addrs represents a number in the range of 0000h to ffffh. er extended addressing register reg reg represents a number in the range of 000h to fffh. im immediate data #data data is a number between 00h to ffh. ir indirect working register @rn n = 0?15. ir indirect register @reg reg. represents a number in the range of 00h to ffh. irr indirect working register pair @rrp p = 0, 2, 4, 6, 8, 10, 12, or 14. irr indirect register pair @reg reg represents an even number in the range 00h to feh p polarity p polarity is a single bit binary value of either 0b or 1b. r working register rn n = 0?15. r register reg reg. represents a number in the range of 00h to ffh.
ps024315-1011 p r e l i m i n a r y ez8 cpu instruction notation z8 encore! xp ? f0823 series product specification 177 table 109 lists additional symbols that are us ed throughout the in struction summary and instruction set description sections. assignment of a value is indicated by an arrow, as shown in the following example. dst dst + src this example indicates that the source data is added to the destina tion data; the result is stored in the destination location. ra relative address x x represents an index in the range of +127 to ?128 which is an offset relative to the address of the next instruction rr working register pair rrp p = 0, 2, 4, 6, 8, 10, 12, or 14. rr register pair reg reg. represents an even number in the range of 00h to feh. vector vector address vector vector represents a number in the range of 00h to ffh. x indexed #index the register or register pair to be indexed is offset by the signed index value (#index) in a +127 to ?128 range. table 109. additional symbols symbol definition dst destination operand src source operand @ indirect address prefix sp stack pointer pc program counter flags flags register rp register pointer # immediate operand prefix b binary number suffix % hexadecimal number prefix h hexadecimal number suffix table 108. notational shorthand (continued) notation description operand range
ps024315-1011 p r e l i m i n a r y ez8 cpu instruction classes z8 encore! xp ? f0823 series product specification 178 ez8 cpu instruction classes ez8 cpu instructions are divided functio nally into the following groups: ? arithmetic ? bit manipulation ? block transfer ? cpu control ? load ? logical ? program control ? rotate and shift ? tables 110 through 117 contain the instructions belonging to each group and the number of operands required for each instruction. some inst ructions appear in more than one table as these instruction can be considered as a subset of more than one category. within these tables, the source operand is identified as ?s rc?, the destination operand is ?dst? and a con- dition code is ?cc?. table 110. arithmetic instructions mnemonic operands instruction adc dst, src add with carry adcx dst, src add with carry using extended addressing add dst, src add addx dst, src add using extended addressing cp dst, src compare cpc dst, src compare with carry cpcx dst, src compare with carry using extended addressing cpx dst, src compare using extended addressing da dst decimal adjust dec dst decrement decw dst decrement word inc dst increment incw dst increment word
ps024315-1011 p r e l i m i n a r y ez8 cpu instruction classes z8 encore! xp ? f0823 series product specification 179 mult dst multiply sbc dst, src subtract with carry sbcx dst, src subtract with carry using extended addressing sub dst, src subtract subx dst, src subtract using extended addressing table 111. bit manipulation instructions mnemonic operands instruction bclr bit, dst bit clear bit p, bit, dst bit set or clear bset bit, dst bit set bswap dst bit swap ccf ? complement carry flag rcf ? reset carry flag scf ? set carry flag tcm dst, src test comp lement under mask tcmx dst, src test complement under mask using extended addressing tm dst, src test under mask tmx dst, src test under mask using extended addressing table 112. block transfer instructions mnemonic operands instruction ldci dst, src load constant to/from program memory and auto- increment addresses ldei dst, src load external data to/from data memory and auto- increment addresses table 110. arithmetic in structions (continued) mnemonic operands instruction
ps024315-1011 p r e l i m i n a r y ez8 cpu instruction classes z8 encore! xp ? f0823 series product specification 180 table 113. cpu control instructions mnemonic operands instruction atm ? atomic execution ccf ? complement carry flag di ? disable interrupts ei ? enable interrupts halt ? halt mode nop ? no operation rcf ? reset carry flag scf ? set carry flag srp src set regi ster pointer stop ? stop mode wdt ? watchdog timer refresh table 114. load instructions mnemonic operands instruction clr dst clear ld dst, src load ldc dst, src load constant to/from program memory ldci dst, src load constant to/from program memory and auto- increment addresses lde dst, src load external data to/from data memory ldei dst, src load external data to/from data memory and auto- increment addresses ldwx dst, src load word using extended addressing ldx dst, src load using extended addressing lea dst, x(src) load effective address pop dst pop popx dst pop using extended addressing push src push pushx src push using extended addressing
ps024315-1011 p r e l i m i n a r y ez8 cpu instruction classes z8 encore! xp ? f0823 series product specification 181 table 115. logical instructions mnemonic operands instruction and dst, src logical and andx dst, src logical and using extended addressing com dst complement or dst, src logical or orx dst, src logical or using extended addressing xor dst, src logical exclusive or xorx dst, src logical exclusive or using extended addressing table 116. program control instructions mnemonic operands instruction brk ? on-chip debugger break btj p, bit, src, da bit test and jump btjnz bit, src, da bit test and jump if non-zero btjz bit, src, da bit test and jump if zero call dst call procedure djnz dst, src, ra decrement and jump non-zero iret ? interrupt return jp dst jump jp cc dst jump conditional jr da jump relative jr cc da jump relative conditional ret ? return trap vector software trap table 117. rotate and shift instructions mnemonic operands instruction bswap dst bit swap rl dst rotate left rlc dst rotate left through carry
ps024315-1011 p r e l i m i n a r y ez8 cpu instruction summary z8 encore! xp ? f0823 series product specification 182 ez8 cpu instruction summary table 118 summarizes the ez8 cpu instruction set. the table identifies the addressing modes employed by the instruction, the effect upon the flags register, the number of cpu clock cycles required for th e instruction fetch, and the number of cpu clock cycles required for the instruction execution. . rr dst rotate right rrc dst rotate right through carry sra dst shift right arithmetic srl dst shift right logical swap dst swap nibbles table 118. ez8 cpu instruction summary assembly ? mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h adc dst, src dst dst + src + c r r 12 * * * * 0 * 2 3 rir 13 2 4 rr 14 3 3 rir 15 3 4 rim 16 3 3 ir im 17 3 4 adcx dst, src dst dst + src + c er er 18 * * * * 0 * 4 3 er im 19 4 3 note: flags notation: * = value is a function of the result of the operation. ? ? = unaffected. ? x = undefined. 0 = reset to 0. ? 1 = set to 1. table 117. rotate and shift instructions (continued) mnemonic operands instruction
ps024315-1011 p r e l i m i n a r y ez8 cpu instruction summary z8 encore! xp ? f0823 series product specification 183 add dst, src dst dst + src r r 02 * * * * 0 * 2 3 rir 03 2 4 rr 04 3 3 rir 05 3 4 rim 06 3 3 ir im 07 3 4 addx dst, src dst dst + src er er 08 * * * * 0 * 4 3 er im 09 4 3 and dst, src dst dst and src r r 52 ? * * 0 ? ? 2 3 rir 53 2 4 rr 54 3 3 rir 55 3 4 rim 56 3 3 ir im 57 3 4 andx dst, src dst dst and src er er 58 ? * * 0 ? ? 4 3 er im 59 4 3 atm block all interrupt and dma requests during execution of the next 3 instructions 2f ?????? 1 2 bclr bit, dst dst[bit] 0 r e2 ?????? 2 2 bit p, bit, dst dst[bit] p r e2 ???0?? 2 2 brk debugger break 00 ? ? ? ? ? ? 1 1 bset bit, dst dst[bit] 1 r e2 ???0?? 2 2 bswap dst dst[7:0] ? dst[0:7] r d5 x * * 0 ? ? 2 2 btj p, bit, src, dst if src[bit] = p ? pc pc + x r f6 ?????? 3 3 ir f7 3 4 table 118. ez8 cpu instruction summary (continued) assembly ? mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h note: flags notation: * = value is a function of the result of the operation. ? ? = unaffected. ? x = undefined. 0 = reset to 0. ? 1 = set to 1.
ps024315-1011 p r e l i m i n a r y ez8 cpu instruction summary z8 encore! xp ? f0823 series product specification 184 btjnz bit, src, dst if src[bit] = 1 ? pc pc + x r f6 ?????? 3 3 ir f7 3 4 btjz bit, src, dst if src[bit] = 0 ? pc pc + x r f6 ?????? 3 3 ir f7 3 4 call dst sp sp ?2 ? @sp pc ? pc dst irr d4 ?????? 2 6 da d6 3 3 ccf c ~c ef *?????- 1 2 clr dst dst 00h r b0 ?????? 2 2 ir b1 2 3 com dst dst ~dst r 60 ? * * 0 ? ? 2 2 ir 61 2 3 cp dst, src dst - src r r a2 * * * * ? ? 2 3 rir a3 2 4 rr a4 3 3 rir a5 3 4 rim a6 3 3 ir im a7 3 4 cpc dst, src dst - src - c r r 1f a2 * * * * ? ? 3 3 rir1f a3 3 4 rr1f a4 4 3 rir1f a5 4 4 rim1f a6 4 3 ir im 1f a7 4 4 cpcx dst, src dst - src - c er er 1f a8 * * * * ? ? 5 3 er im 1f a9 5 3 cpx dst, src dst - src er er a8 * * * * ? ? 4 3 er im a9 4 3 table 118. ez8 cpu instruction summary (continued) assembly ? mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h note: flags notation: * = value is a function of the result of the operation. ? ? = unaffected. ? x = undefined. 0 = reset to 0. ? 1 = set to 1.
ps024315-1011 p r e l i m i n a r y ez8 cpu instruction summary z8 encore! xp ? f0823 series product specification 185 da dst dst da(dst) r 40 * * * x ? ? 2 2 ir 41 2 3 dec dst dst dst - 1 r 30 ? * * * ? ? 2 2 ir 31 2 3 decw dst dst dst - 1 rr 80 ? * * * ? ? 2 5 irr 81 2 6 di irqctl[7] ? 0 8f ?????? 1 2 djnz dst, ra dst ? dst ? 1 ? if dst ? 0 ? pc ? pc + x r 0a-fa ?????? 2 3 ei irqctl[7] ? 1 9f ?????? 1 2 halt halt mode 7f ?????? 1 2 inc dst dst ? dst + 1 r 20 ? * * ? ? ? 2 2 ir 21 2 3 r0 e - f e 12 incw dst dst ? dst + 1 rr a0 ? * * * ? ? 2 5 irr a1 2 6 iret flags ? @sp ? sp ? sp + 1 ? pc ? @sp ? sp ? sp + 2 ? irqctl[7] ? 1 bf ****** 1 5 jp dst pc ? dst da 8d ?????? 3 2 irr c4 2 3 jp cc, dst if cc is true ? pc ? dst da 0d-fd ?????? 3 2 jr dst pc ? pc + x da 8b ?????? 2 2 jr cc, dst if cc is true ? pc ? pc + x da 0b-fb ?????? 2 2 table 118. ez8 cpu instruction summary (continued) assembly ? mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h note: flags notation: * = value is a function of the result of the operation. ? ? = unaffected. ? x = undefined. 0 = reset to 0. ? 1 = set to 1.
ps024315-1011 p r e l i m i n a r y ez8 cpu instruction summary z8 encore! xp ? f0823 series product specification 186 ld dst, rc dst ? src r im 0c-fc ?????? 2 2 rx(r) c7 3 3 x(r) r d7 3 4 rir e3 2 3 rr e4 3 2 rir e5 3 4 rim e6 3 2 ir im e7 3 3 ir r f3 2 3 ir r f5 3 3 ldc dst, src dst ? src r irr c2 ?????? 2 5 ir irr c5 2 9 irr r d2 2 5 ldci dst, src dst ? src ? r ? r + 1 ? rr ? rr + 1 ir irr c3 ?????? 2 9 irr ir d3 2 9 lde dst, src dst ? src r irr 82 ?????? 2 5 irr r 92 2 5 ldei dst, src dst ? src ? r ? r + 1 ? rr ? rr + 1 ir irr 83 ?????? 2 9 irr ir 93 2 9 ldwx dst, src dst ? src er er 1fe8 ?????? 5 4 table 118. ez8 cpu instruction summary (continued) assembly ? mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h note: flags notation: * = value is a function of the result of the operation. ? ? = unaffected. ? x = undefined. 0 = reset to 0. ? 1 = set to 1.
ps024315-1011 p r e l i m i n a r y ez8 cpu instruction summary z8 encore! xp ? f0823 series product specification 187 ldx dst, src dst ? src r er 84 ?????? 3 2 ir er 85 3 3 rirr 86 3 4 ir irr 87 3 5 r x(rr) 88 3 4 x(rr) r 89 3 4 er r 94 3 2 er ir 95 3 3 irr r 96 3 4 irr ir 97 3 5 er er e8 4 2 er im e9 4 2 lea dst, x(src) dst ? src + x r x(r) 98 ?????? 3 3 rr x(rr) 99 3 5 mult dst dst[15:0] ? ? dst[15:8] * dst[7:0] rr f4 ?????? 2 8 nop no operation 0f ? ? ? ? ? ? 1 2 or dst, src dst ? dst or src r r 42 ? * * 0 ? ? 2 3 rir 43 2 4 rr 44 3 3 rir 45 3 4 rim 46 3 3 ir im 47 3 4 orx dst, src dst ? dst or src er er 48 ? * * 0 ? ? 4 3 er im 49 4 3 pop dst dst ? @sp ? sp ? sp + 1 r 50 ?????? 2 2 ir 51 2 3 table 118. ez8 cpu instruction summary (continued) assembly ? mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h note: flags notation: * = value is a function of the result of the operation. ? ? = unaffected. ? x = undefined. 0 = reset to 0. ? 1 = set to 1.
ps024315-1011 p r e l i m i n a r y ez8 cpu instruction summary z8 encore! xp ? f0823 series product specification 188 popx dst dst ? @sp sp ? sp + 1 er d8 ?????? 3 2 push src sp ? sp ? 1 @sp ? src r 70 ?????? 2 2 ir 71 2 3 im if70 3 2 pushx src sp ? sp ? 1 ? @sp ? src er c8 ?????? 3 2 rcf c ? 0 cf 0????? 1 2 ret pc ? @sp ? sp ? sp + 2 af ?????? 1 4 rl dst r 90 * * * * ? ? 2 2 ir 91 2 3 rlc dst r 10 * * * * ? ? 2 2 ir 11 2 3 rr dst r e0 ****?? 2 2 ir e1 2 3 rrc dst r c0 * * * * ? ? 2 2 ir c1 2 3 table 118. ez8 cpu instruction summary (continued) assembly ? mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h note: flags notation: * = value is a function of the result of the operation. ? ? = unaffected. ? x = undefined. 0 = reset to 0. ? 1 = set to 1. d7 d6 d5 d4 d3 d2 d1 d0 dst c d7 d6 d5 d4 d3 d2 d1 d0 dst c d7 d6 d5 d4 d3 d2 d1 d0 dst c d7 d6 d5 d4 d3 d2 d1 d0 dst c
ps024315-1011 p r e l i m i n a r y ez8 cpu instruction summary z8 encore! xp ? f0823 series product specification 189 sbc dst, src dst ? dst ? src - c r r 32 * * * * 1 * 2 3 rir 33 2 4 rr 34 3 3 rir 35 3 4 rim 36 3 3 ir im 37 3 4 sbcx dst, src dst ? dst ? src - c er er 38 * * * * 1 * 4 3 er im 39 4 3 scf c ? 1 df 1????? 1 2 sra dst r d0 * * * 0 ? ? 2 2 ir d1 2 3 srl dst r 1f c0 * * 0 * ? ? 3 2 ir 1f c1 3 3 srp src rp ? src im 01 ?????? 2 2 stop stop mode 6f ?????? 1 2 sub dst, src dst ? dst ? src r r 22 * * * * 1 * 2 3 rir 23 2 4 rr 24 3 3 rir 25 3 4 rim 26 3 3 ir im 27 3 4 subx dst, src dst ? dst ? src er er 28 * * * * 1 * 4 3 er im 29 4 3 swap dst dst[7:4] ? dst[3:0] r f0 x * * x ? ? 2 2 ir f1 2 3 table 118. ez8 cpu instruction summary (continued) assembly ? mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h note: flags notation: * = value is a function of the result of the operation. ? ? = unaffected. ? x = undefined. 0 = reset to 0. ? 1 = set to 1. d7 d6 d5 d4 d3 d2 d1 d0 dst c d7 d6 d5 d4 d3 d2 d1 d0 dst c 0
ps024315-1011 p r e l i m i n a r y ez8 cpu instruction summary z8 encore! xp ? f0823 series product specification 190 tcm dst, src (not dst) and src r r 62 ? * * 0 ? ? 2 3 rir 63 2 4 rr 64 3 3 rir 65 3 4 rim 66 3 3 ir im 67 3 4 tcmx dst, src (not dst) and src er er 68 ? * * 0 ? ? 4 3 er im 69 4 3 tm dst, src dst and src r r 72 ? * * 0 ? ? 2 3 rir 73 2 4 rr 74 3 3 rir 75 3 4 rim 76 3 3 ir im 77 3 4 tmx dst, src dst and src er er 78 ? * * 0 ? ? 4 3 er im 79 4 3 trap vector sp ? sp ? 2 ? @sp ? pc ? sp ? sp ? 1 ? @sp ? flags ? pc ? @vector vector f2 ?????? 2 6 wdt 5f ?????? 1 2 table 118. ez8 cpu instruction summary (continued) assembly ? mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h note: flags notation: * = value is a function of the result of the operation. ? ? = unaffected. ? x = undefined. 0 = reset to 0. ? 1 = set to 1.
ps024315-1011 p r e l i m i n a r y ez8 cpu instruction summary z8 encore! xp ? f0823 series product specification 191 xor dst, src dst ? dst xor src r r b2 ? * * 0 ? ? 2 3 rir b3 2 4 rr b4 3 3 rir b5 3 4 rim b6 3 3 ir im b7 3 4 xorx dst, src dst ? dst xor src er er b8 ? * * 0 ? ? 4 3 er im b9 4 3 table 118. ez8 cpu instruction summary (continued) assembly ? mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h note: flags notation: * = value is a function of the result of the operation. ? ? = unaffected. ? x = undefined. 0 = reset to 0. ? 1 = set to 1.
ps024315-1011 p r e l i m i n a r y opcode maps z8 encore! xp ? f0823 series product specification 192 opcode maps a description of the opcode map data and the abbreviations are provided in figure 26. figures 27 and 28 provide information about each of the ez8 cpu instructions. table 119 lists opcode map abbreviations. figure 26. opcode map cell description cp 3.3 r2,r1 a 4 opcode lower nibble second operand after assembly first operand after assembly opcode upper nibble instruction cycles fetch cycles
ps024315-1011 p r e l i m i n a r y opcode maps z8 encore! xp ? f0823 series product specification 193 table 119. opcode map abbreviations abbreviation description abbreviation description b bit position irr indirect register pair cc condition code p polarity (0 or 1) x 8-bit signed index or displace- ment r 4-bit working register da destination address r 8-bit register er extended addressing register r1, r1, ir1, irr1, ir1, rr1, rr1, irr1, er1 destination address im immediate data value r2, r2, ir2, irr2, ir2, rr2, rr2, irr2, er2 source address ir indirect working register ra relative ir indirect register rr working register pair irr indirect working register pair rr register pair
ps024315-1011 p r e l i m i n a r y opcode maps z8 encore! xp ? f0823 series product specification 194 figure 27. first opcode map cp 3.3 r2,r1 cp 3.4 ir2,r1 cp 2.3 r1,r2 cp 2.4 r1,ir2 cpx 4.3 er2,er1 cpx 4.3 im,er1 cp 3.3 r1,im cp 3.4 ir1,im rrc 2.2 r1 rrc 2.3 ir1 0 1 2 3 4 5 6 7 8 9abcde f 0 1 2 3 4 5 6 7 8 9 a b c d e f lower nibble (hex) upper nibble (hex) brk 1.1 srp 2.2 im add 2.3 r1,r2 add 2.4 r1,ir2 add 3.3 r2,r1 add 3.4 ir2,r1 add 3.3 r1,im add 3.4 ir1,im addx 4.3 er2,er1 addx 4.3 im,er1 djnz 2.3 r1,x jr 2.2 cc,x ld 2.2 r1,im jp 3.2 cc,da inc 1.2 r1 nop 1.2 rlc 2.2 r1 rlc 2.3 ir1 adc 2.3 r1,r2 adc 2.4 r1,ir2 adc 3.3 r2,r1 adc 3.4 ir2,r1 adc 3.3 r1,im adc 3.4 ir1,im adcx 4.3 er2,er1 adcx 4.3 im,er1 inc 2.2 r1 inc 2.3 ir1 sub 2.3 r1,r2 sub 2.4 r1,ir2 sub 3.3 r2,r1 sub 3.4 ir2,r1 sub 3.3 r1,im sub 3.4 ir1,im subx 4.3 er2,er1 subx 4.3 im,er1 dec 2.2 r1 dec 2.3 ir1 sbc 2.3 r1,r2 sbc 2.4 r1,ir2 sbc 3.3 r2,r1 sbc 3.4 ir2,r1 sbc 3.3 r1,im sbc 3.4 ir1,im sbcx 4.3 er2,er1 sbcx 4.3 im,er1 da 2.2 r1 da 2.3 ir1 or 2.3 r1,r2 or 2.4 r1,ir2 or 3.3 r2,r1 or 3.4 ir2,r1 or 3.3 r1,im or 3.4 ir1,im orx 4.3 er2,er1 orx 4.3 im,er1 pop 2.2 r1 pop 2.3 ir1 and 2.3 r1,r2 and 2.4 r1,ir2 and 3.3 r2,r1 and 3.4 ir2,r1 and 3.3 r1,im and 3.4 ir1,im andx 4.3 er2,er1 andx 4.3 im,er1 com 2.2 r1 com 2.3 ir1 tcm 2.3 r1,r2 tcm 2.4 r1,ir2 tcm 3.3 r2,r1 tcm 3.4 ir2,r1 tcm 3.3 r1,im tcm 3.4 ir1,im tcmx 4.3 er2,er1 tcmx 4.3 im,er1 push 2.2 r2 push 2.3 ir2 tm 2.3 r1,r2 tm 2.4 r1,ir2 tm 3.3 r2,r1 tm 3.4 ir2,r1 tm 3.3 r1,im tm 3.4 ir1,im tmx 4.3 er2,er1 tmx 4.3 im,er1 decw 2.5 rr1 decw 2.6 irr1 lde 2.5 r1,irr2 ldei 2.9 ir1,irr2 ldx 3.2 r1,er2 ldx 3.3 ir1,er2 ldx 3.4 irr2,r1 ldx 3.5 irr2,ir1 ldx 3.4 r1,rr2,x ldx 3.4 rr1,r2,x rl 2.2 r1 rl 2.3 ir1 lde 2.5 r2,irr1 ldei 2.9 ir2,irr1 ldx 3.2 r2,er1 ldx 3.3 ir2,er1 ldx 3.4 r2,irr1 ldx 3.5 ir2,irr1 lea 3.3 r1,r2,x lea 3.5 rr1,rr2,x incw 2.5 rr1 incw 2.6 irr1 clr 2.2 r1 clr 2.3 ir1 xor 2.3 r1,r2 xor 2.4 r1,ir2 xor 3.3 r2,r1 xor 3.4 ir2,r1 xor 3.3 r1,im xor 3.4 ir1,im xorx 4.3 er2,er1 xorx 4.3 im,er1 ldc 2.5 r1,irr2 ldci 2.9 ir1,irr2 ldc 2.5 r2,irr1 ldci 2.9 ir2,irr1 jp 2.3 irr1 ldc 2.9 ir1,irr2 ld 3.4 r1,r2,x pushx 3.2 er2 sra 2.2 r1 sra 2.3 ir1 popx 3.2 er1 ld 3.4 r2,r1,x call 2.6 irr1 bswap 2.2 r1 call 3.3 da ld 3.2 r2,r1 ld 3.3 ir2,r1 bit 2.2 p,b,r1 ld 2.3 r1,ir2 ldx 4.2 er2,er1 ldx 4.2 im,er1 ld 3.2 r1,im ld 3.3 ir1,im rr 2.2 r1 rr 2.3 ir1 mult 2.8 rr1 ld 3.3 r2,ir1 trap 2.6 vector ld 2.3 ir1,r2 btj 3.3 p,b,r1,x btj 3.4 p,b,ir1,x swap 2.2 r1 swap 2.3 ir1 rcf 1.2 wdt 1.2 stop 1.2 halt 1.2 di 1.2 ei 1.2 ret 1.4 iret 1.5 scf 1.2 ccf 1.2 opcode see 2nd map 1
ps024315-1011 p r e l i m i n a r y opcode maps z8 encore! xp ? f0823 series product specification 195 figure 28. second opcode map after 1fh cpc 4.3 r2,r1 cpc 4.4 ir2,r1 cpc 3.3 r1,r2 cpc 3.4 r1,ir2 cpcx 5.3 er2,er1 cpcx 5.3 im,er1 cpc 4.3 r1,im cpc 4.4 ir1,im srl 3.2 r1 srl 3.3 ir1 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 1 2 3 4 5 6 7 8 9 a b c d e f lower nibble (hex) upper nibble (hex) 3 , ldwx 5, 4 er2,er1
ps024315-1011 p r e l i m i n a r y electrical characteristics z8 encore! xp ? f0823 series product specification 196 electrical characteristics the data in this chapter represents all known data prior to qualifi cation and characteriza- tion of the f0823 series of pr oducts, and is therefore subject to change. additional electri- cal characteristics may be found in the individual chapters of this document. absolute maximum ratings stresses greater than those listed in table 12 0 may cause permanent damage to the device. these ratings are stress ratings only. operation of the device at any condition outside those indicated in the operational s ections of these specifications is not implied. exposure to absolute maximum rating cond itions for extended periods may affect device reliability. for improved reliability, tie unused in puts to one of the supply voltages (v dd or v ss ). table 120. absolute maximum ratings parameter minimum maximum units notes ambient temperature under bias ?40 +105 c storage temperature ?65 +150 c voltage on any pin with respect to v ss ?0.3 +5.5 v 1 ?0.3 +3.9 v 2 voltage on v dd pin with respect to v ss ?0.3 +3.6 v maximum current on input and/or inactive output pin ?5 +5 a maximum output current from active output pin ?25 +25 ma 8-pin packages maximum ratings at 0c to 70c total power dissipation 220 mw maximum current into v dd or out of v ss 60 ma 20-pin packages maximum ratings at 0c to 70c total power dissipation 430 mw maximum current into v dd or out of v ss 120 ma 28-pin packages maximum ratings at 0c to 70c total power dissipation 450 mw maximum current into v dd or out of v ss 125 ma notes: operating temper ature is specified in dc characteristics. 1. this voltage applies to all pins except the following: v dd , av dd , pins supporting analog input (port b[5:0], port c[2:0]) and pins supporting the crystal oscillator (pa0 and pa1). on the 8-pin packages, this applies to all pins but v dd . 2. this voltage applies to pins on the 20/28 pin packages supporting analog input (port b[5:0], port c[2:0]) and pins supporting the crystal oscillator (pa0 and pa1).
ps024315-1011 p r e l i m i n a r y dc characteristics z8 encore! xp ? f0823 series product specification 197 dc characteristics table 121 lists the dc characteristics of th e z8 encore! xp f0823 series products. all voltages are referenced to v ss , the primary system ground. table 121. dc characteristics symbol parameter t a = ?40c to +105c (unless otherwise specified) units conditions minimum typical maximum v dd supply voltage 2.7 ? 3.6 v v il1 low level input voltage ?0.3 ? 0.3*v dd v v ih1 high level input voltage 0.7*v dd ? 5.5 v for all input pins without analog or oscillator function. for all sig- nal pins on the 8-pin devices. programmable pull-ups must also be disabled. v ih2 high level input voltage 0.7*v dd ?v dd +0.3 v for those pins with analog or oscillator function (20-/28-pin devices only), or when pro- grammable pull-ups are enabled. v ol1 low level output voltage ??0.4vi ol = 2 ma; v dd = 3.0 v ? high output drive disabled. v oh1 high level output voltage 2.4 ? ? v i oh = ?2 ma; v dd = 3.0 v ? high output drive disabled. v ol2 low level output voltage ??0.6vi ol = 20 ma; v dd = 3.3 v ? high output drive enabled. v oh2 high level output voltage 2.4 ? ? v i oh = ?20 ma; v dd = 3.3 v ? high output drive enabled. i ih input leakage cur- rent ?+ 0.002 + 5av in = v dd v dd = 3.3 v i il input leakage cur- rent ?+ 0.007 + 5av in = v ss v dd = 3.3 v i tl tristate leakage current ??+ 5a notes: 1. this condition excludes all pins that have on-chip pull-ups, when driven low. 2. these values are provided for design guid ance only and are not tested in production.
ps024315-1011 p r e l i m i n a r y dc characteristics z8 encore! xp ? f0823 series product specification 198 i led controlled current drive 1.8 3 4.5 ma {afs2,afs1} = {0,0}. 2.8 7 10.5 ma {afs2,afs1} = {0,1}. 7.8 13 19.5 ma {afs2,afs1} = {1,0}. 12 20 30 ma {afs2,afs1} = {1,1}. c pad gpio port pad capacitance ?8.0 2 ?pf c xin x in pad capaci- tance ?8.0 2 ?pf c xout x out pad capaci- tance ?9.5 2 ?pf i pu weak pull-up cur- rent 30 100 350 a v dd = 3.0 v?3.6 v. v ram ram data reten- tion voltage tbd v voltage at which ram retains static values; no reading or writ- ing is allowed. table 121. dc characteristics (continued) symbol parameter t a = ?40c to +105c (unless otherwise specified) units conditions minimum typical maximum notes: 1. this condition excludes all pins that have on-chip pull-ups, when driven low. 2. these values are provided for design guid ance only and are not tested in production.
ps024315-1011 p r e l i m i n a r y dc characteristics z8 encore! xp ? f0823 series product specification 199 table 122. power consumption symbol parameter v dd = 2.7 v to 3.6 v units conditions typical 1 maximum 2 std temp maximum 3 ext temp i dd stop supply current in stop mode 0.1 2 7.5 a no peripherals enabled. all pins driven to v dd or v ss . i dd halt supply current in halt mode (with all peripher- als disabled) 35 55 65 a 32 khz. 520 630 700 a 5.5 mhz. i dd supply current in active mode (with all peripherals disabled) 2.8 4.5 4.8 ma 32 khz. 4.5 5.2 5.2 ma 5.5 mhz. i dd wdt watchdog timer sup- ply current 0.9 1.0 1.1 a i dd ipo internal precision oscil- lator supply current 350 500 550 a i dd vbo voltage brown-out sup- ply current 50 a for 20-/28-pin devices (vbo only). 4 for 8-pin devices. 4 i dd adc analog-to-digital con- verter supply current (with external refer- ence) 2.8 3.1 3.2 ma 32 khz. 3.1 3.6 3.7 ma 5.5 mhz. 3.3 3.7 3.8 ma 10 mhz. 3.7 4.2 4.3 ma 20 mhz. i dd adcref adc internal refer- ence supply current 0 a see note 4. i dd cmp comparator supply cur- rent 150 180 190 a see note 4. i dd bg band gap supply cur- rent 320 480 500 a for 20-/28-pin devices. for 8-pin devices. notes: 1. typical conditions are defined as v dd = 3.3 v and +30c. 2. standard temperature is defined as t a = 0c to +70c; these values not tested in production for worst case behavior, but are derived from product characterization and provided for design guidance only. 3. extended temperature is defined as t a = ?40c to +105c; these values not tested in production for worst case behavior, but are derived from product characterization and provided for design guidance only. 4. for this block to operate, the band gap circuit is automatically turned on and must be added to the total supply current. this bandgap current is only added once, regardless of how many peripherals are using it.
ps024315-1011 p r e l i m i n a r y ac characteristics z8 encore! xp ? f0823 series product specification 200 ac characteristics the section provides information about the ac characteristics and timing. all ac timing information assumes a standard load of 50 pf on all outputs. table 123. ac characteristics symbol parameter v dd = 2.7 v to 3.6 v t a = ?40c to +105c (unless otherwise stated) units conditions minimum maximum f sysclk system clock frequency ? 20.0* mhz read-only from flash memory. 0.032768 20.0 1 mhz program or erasure of the flash memory. t xin system clock period 50 ? ns t clk = 1/f sysclk . t xinh system clock high time 20 30 ns t clk = 50 ns. t xinl system clock low time 20 30 ns t clk = 50 ns. t xinr system clock rise time ? 3 ns t clk = 50 ns. t xinf system clock fall time ? 3 ns t clk = 50 ns. note: *system clock frequency is limited by the internal precision oscillator on the z8 encore! xp f0823 series. see table 124 on page 200. table 124. internal precision osci llator electrical characteristics symbol parameter v dd = 2.7 v to 3.6 v t a = ?40c to +105c (unless otherwise stated) units conditions minimum typical maximum f ipo internal precision oscillator frequency (high speed) 5.53 mhz v dd = 3.3 v t a = 30c f ipo internal precision oscillator frequency (low speed) 32.7 khz v dd = 3.3 v t a = 30c f ipo internal precision oscillator error + 1+ 4% t ipost internal precision oscillator startup time 3s
ps024315-1011 p r e l i m i n a r y on-chip peripheral ac and dc electrical z8 encore! xp ? f0823 series product specification 201 on-chip peripheral ac and dc electrical characteristics table 125 tabulates the electrical characteristics of the por and vbo blocks. table 125. power-on reset and voltage brow n-out electrical characteristics and timing symbol parameter t a = ?40c to +105c units conditions minimum typical* maximum v por power-on reset voltage threshold 2.20 2.45 2.70 v v dd = v por v vbo voltage brown-out reset volt- age threshold 2.15 2.40 2.65 v v dd = v vbo v por to v vbo hysteresis 50 75 mv starting v dd voltage to ensure valid power- on reset. ?v ss ?v t ana power-on reset analog delay ? 70 ? s v dd > v por ; t por digital reset delay fol- lows t ana t por power-on reset digital de lay 16 s 66 internal preci- sion oscillator cycles + ipo startup time (t ipost ) t smr stop mode recovery 16 s 66 internal preci- sion oscillator cycles t vbo voltage brown-out pulse rejection period ? 10 ? s period of time in which v dd < v vbo without generating a reset. t ramp time for v dd to transition from v ss to v por to ensure valid reset 0.10 ? 100 ms t smp stop mode recovery pin pulse rejection period 20 ns for any smr pin or for the reset pin when it is asserted in stop mode. note: *data in the typical column is from characterization at 3.3 v and 30c. these values are provided for design guidance only and are not tested in production.
ps024315-1011 p r e l i m i n a r y on-chip peripheral ac and dc electrical z8 encore! xp ? f0823 series product specification 202 table 126. flash memory electr ical characteristics and timing parameter v dd = 2.7 v to 3.6 v t a = ?40c to +105c (unless otherwise stated) units notes minimum typical maximum flash byte read time 100 ? ? ns flash byte program time 20 ? 40 s flash page erase time 10 ? ? ms flash mass erase time 200 ? ? ms writes to single address before next erase ??2 flash row program time ? ? 8 ms cumulative program time for single row cannot exceed limit before next erase. this param- eter is only an issue when bypassing the flash controller. data retention 100 ? ? years 25c endurance 10,000 ? ? cycles program/erase cycles table 127. watchdog timer electrical characteristics and timing symbol parameter v dd = 2.7 v to 3.6 v t a = ?40c to +105c (unless otherwise stated) units conditions minimum typical maximum f wdt wdt oscillator frequency 10 khz f wdt wdt oscillator error + 50 % t wdt- cal wdt calibrated timeout 0.98 1 1.02 s v dd = 3.3 v; t a = 30c 0.70 1 1.30 s v dd = 2.7 v to 3.6 v t a = 0c to 70c 0.50 1 1.50 s v dd = 2.7 v to 3.6 v t a = ?40c to +105c
ps024315-1011 p r e l i m i n a r y on-chip peripheral ac and dc electrical z8 encore! xp ? f0823 series product specification 203 table 128. analog-to-digital converter electrical characteristics and timing symbol parameter v dd = 3.0 v to 3.6 v t a = 0c to +70c (unless otherwise stated) units conditions minimum typical maximum resolution 10 ? bits differential nonlinearity (dnl) ?1.0 ? 1.0 lsb 3 external v ref = 2.0 v; ? r s 3.0 k ? integral nonlinearity (inl) ?3.0 ? 3.0 lsb 3 external v ref = 2.0 v; ? r s 3.0 k ? offset error with calibration + 1l s b 3 absolute accuracy with calibration + 3l s b 3 v ref internal reference voltage 1.0 2.0 1.1 2.2 1.2 2.4 v refsel=01 refsel=10 v ref internal reference varia- tion with temperature + 1.0 % temperature variation with v dd = 3.0 v ref internal reference voltage variation with v dd + 0.5 % supply voltage varia- tion with t a = 30c r re- fout reference buffer output impedance 850 w when the internal ref- erence is buffered and driven out to the vref pin (refout = 1) single-shot conversion time ? 5129 ? sys- tem clock cycles all measurements but temperature sensor 10258 temperature sensor measurement continuous conversion time ? 256 ? sys- tem clock cycles all measurements but temperature sensor 512 temperature sensor measurement notes: 1. analog source impedance affects the adc offset voltage (because of pin leakage) and input settling time. 2. devices are factory calibrated at v dd = 3.3 v and t a = +30c, so the adc is maximally accurate under these conditions. 3. lsbs are defined assuming 10-bit resolution. 4. this is the maximum recommended resistance seen by the adc input pin. 5. the input impedance is inversely proportional to the system clock frequency.
ps024315-1011 p r e l i m i n a r y on-chip peripheral ac and dc electrical z8 encore! xp ? f0823 series product specification 204 general purpose i/o port input data sample timing figure 29 displays a timing sequence for the gpio port input sampling. the input value on a gpio port pin is sampled on the rising edge of the system clock. the port value is signal input bandwidth ? 10 khz as defined by ?3 db point r s analog source impedance 4 ? ? 10 kw in unbuffered mode zin input impedance ? 150 kw in unbuffered mode at 20 mhz 5 vin input voltage range 0 v dd v unbuffered mode table 129. comparator electrical characteristics symbol parameter v dd = 2.7 v to 3.6 v t a = ?40c to +105c units conditions minimum typical maximum v os input dc offset 5 mv v cref programmable internal reference voltage + 5 % 20-/28-pin devices + 3 % 8-pin devices t prop propagation delay 200 ns v hys input hysteresis 4 mv v in input voltage range v ss v dd ?1 v table 128. analog-to-digital converter electr ical characteristics and timing (continued) symbol parameter v dd = 3.0 v to 3.6 v t a = 0c to +70c (unless otherwise stated) units conditions minimum typical maximum notes: 1. analog source impedance affects the adc offset voltage (because of pin leakage) and input settling time. 2. devices are factory calibrated at v dd = 3.3 v and t a = +30c, so the adc is maximally accurate under these conditions. 3. lsbs are defined assuming 10-bit resolution. 4. this is the maximum recommended resistance seen by the adc input pin. 5. the input impedance is inversely proportional to the system clock frequency.
ps024315-1011 p r e l i m i n a r y on-chip peripheral ac and dc electrical z8 encore! xp ? f0823 series product specification 205 available to the ez8 cpu on the second rising clock edge following the change of the port value. figure 29. port input sample timing table 130. gpio port input timing parameter abbreviation delay (ns) minimum maximum t s_port port input transition to x in rise setup time (not pictured) 5 ? t h_port x in rise to port input transition hold time (not pictured) 0 ? t smr gpio port pin pulse width to en sure stop mode recovery (for gpio port pins enabled as smr sources) 1 ? s system tclk port pin port value changes to 0 0 latched into port input input value port input data register latch clock data register port input data read on data bus port input data register value 0 read by ez8
ps024315-1011 p r e l i m i n a r y on-chip peripheral ac and dc electrical z8 encore! xp ? f0823 series product specification 206 general purpose i/o port output timing figure 30 and table 131 provide timing information for gpio port pins. figure 30. gpio port output timing table 131. gpio port output timing parameter abbreviation delay (ns) minimum maximum gpio port pins t 1 x in rise to port output valid delay ? 15 t 2 x in rise to port output hold time 2 ? x in port output tclk t1 t2
ps024315-1011 p r e l i m i n a r y on-chip peripheral ac and dc electrical z8 encore! xp ? f0823 series product specification 207 on-chip debugger timing figure 31 and table 132 provide timing info rmation for the dbg pin. the dbg pin tim- ing specifications assume a 4 ns maximum rise and fall time. figure 31. on-chip debugger timing table 132. on-chip debugger timing parameter abbreviation delay (ns) minimum maximum dbg t 1 x in rise to dbg valid delay ? 15 t 2 x in rise to dbg output hold time 2 ? t 3 dbg to x in rise input setup time 5 ? t 4 dbg to x in rise input hold time 5 ? x in dbg tclk t1 t2 (output) dbg t3 t4 (input) output data input data
ps024315-1011 p r e l i m i n a r y on-chip peripheral ac and dc electrical z8 encore! xp ? f0823 series product specification 208 uart timing figure 32 and table 133 provide timing info rmation for uart pins for the case where cts is used for flow control. the cts to de assertion delay (t1) assumes the transmit data register has been loaded with data prior to cts assertion. figure 32. uart timing with cts table 133. uart timing with cts parameter abbreviation delay (ns) minimum maximum uart t 1 cts fall to de output delay 2 * x in period 2 * x in period + 1 bit time t 2 de assertion to txd falling edge (start bit) delay 5 t 3 end of stop bit(s) to de deassertion delay 5 cts de t1 (output) txd t2 (output) (input) start bit 0 bit 1 bit 7 parity stop end of stop bit(s) t3
ps024315-1011 p r e l i m i n a r y on-chip peripheral ac and dc electrical z8 encore! xp ? f0823 series product specification 209 figure 33 and table 134 provide timing info rmation for uart pins for the case where cts is not used for flow contro l. de asserts after the transmit data register has been writ- ten. de remains asserted for mu ltiple characters as long as the transmit data register is written with the next character before the current character has completed. figure 33. uart timing without cts table 134. uart timing without cts parameter abbreviation delay (ns) minimum maximum uart t 1 de assertion to txd falling edge (start bit) delay 1 * x in period 1 bit time t 2 end of stop bit(s) to de deassertion delay (tx data register is empty) 5 de t1 (output) txd t2 (output) start bit0 bit 1 bit 7 parity stop end of stop bit(s)
ps024315-1011 p r e l i m i n a r y packaging z8 encore! xp ? f0823 series product specification 210 packaging zilog?s f0823 series of mcus includes the z8f0113, z8f0123, z8f0213, z8f0223, z8f0413, z8f0423, z8f0813 and Z8F0823 devi ces, which are available in the following packages: ? 8-pin plastic dual inline package (pdip) ? 8-pin quad flat no-lead package (qfn)/mlf-s 1 ? 20-pin plastic dual -inline package (pdip) ? 20-pin small outline integrated circuit package (soic) ? 20-pin small shrink outline package (ssop) ? 28-pin plastic dual -inline package (pdip) ? 28-pin small outline integrated circuit package (soic) ? 28-pin small shrink outline package (ssop) ? current diagrams for each of the se packages are published in zilog?s packaging product specification (ps0072) , which is available free for do wnload from the zilog website. 1. the footprint of the qfn)/mlf-s packag e is identical to that of the 8-pin so ic package, but with a lower profile.
ps024315-1011 p r e l i m i n a r y ordering information z8 encore! xp ? f0823 series product specification 211 ordering information order your f0823 series products from zilog using the part numbers shown in table 135. for more information about ordering, please consult your local zilog sales office. the sales location page on the zilog website lists all regional offices. table 135. z8 encore! xp f0823 series ordering matrix part number flash ram i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels uart with irda description z8 encore! xp f0823 series with 8 kb fl ash, 10-bit analog-to-digital converter standard temperature: 0c to 70c Z8F0823pb005sg 8 kb 1 kb 6 12 2 4 1 pdip 8-pin package Z8F0823qb005sg 8 kb 1 kb 6 12 2 4 1 qfn 8-pin package Z8F0823sb005sg 8 kb 1 kb 6 12 2 4 1 soic 8-pin package Z8F0823sh005sg 8 kb 1 kb 16 18 2 7 1 soic 20-pin package Z8F0823hh005sg 8 kb 1 kb 16 18 2 7 1 ssop 20-pin package Z8F0823ph005sg 8 kb 1 kb 16 18 2 7 1 pdip 20-pin package Z8F0823sj005sg 8 kb 1 kb 22 18 2 8 1 soic 28-pin package Z8F0823hj005sg 8 kb 1 kb 22 18 2 8 1 ssop 28-pin package Z8F0823pj005sg 8 kb 1 kb 22 18 2 8 1 pdip 28-pin package extended temperature: ?40c to 105c Z8F0823pb005eg 8 kb 1 kb 6 12 2 4 1 pdip 8-pin package Z8F0823qb005eg 8 kb 1 kb 6 12 2 4 1 qfn 8-pin package Z8F0823sb005eg 8 kb 1 kb 6 12 2 4 1 soic 8-pin package Z8F0823sh005eg 8 kb 1 kb 16 18 2 7 1 soic 20-pin package Z8F0823hh005eg 8 kb 1 kb 16 18 2 7 1 ssop 20-pin package Z8F0823ph005eg 8 kb 1 kb 16 18 2 7 1 pdip 20-pin package Z8F0823sj005eg 8 kb 1 kb 22 18 2 8 1 soic 28-pin package Z8F0823hj005eg 8 kb 1 kb 22 18 2 8 1 ssop 28-pin package Z8F0823pj005eg 8 kb 1 kb 22 18 2 8 1 pdip 28-pin package
ps024315-1011 p r e l i m i n a r y ordering information z8 encore! xp ? f0823 series product specification 212 z8 encore! xp f0823 series with 8 kb flash standard temperature: 0c to 70c z8f0813pb005sg 8 kb 1 kb 6 12 2 0 1 pdip 8-pin package z8f0813qb005sg 8 kb 1 kb 6 12 2 0 1 qfn 8-pin package z8f0813sb005sg 8 kb 1 kb 6 12 2 0 1 soic 8-pin package z8f0813sh005sg 8 kb 1 kb 16 18 2 0 1 soic 20-pin package z8f0813hh005sg 8 kb 1 kb 16 18 2 0 1 ssop 20-pin package z8f0813ph005sg 8 kb 1 kb 16 18 2 0 1 pdip 20-pin package z8f0813sj005sg 8 kb 1 kb 24 18 2 0 1 soic 28-pin package z8f0813hj005sg 8 kb 1 kb 24 18 2 0 1 ssop 28-pin package z8f0813pj005sg 8 kb 1 kb 24 18 2 0 1 pdip 28-pin package extended temperature: ?40c to 105c z8f0813pb005eg 8 kb 1 kb 6 12 2 0 1 pdip 8-pin package z8f0813qb005eg 8 kb 1 kb 6 12 2 0 1 qfn 8-pin package z8f0813sb005eg 8 kb 1 kb 6 12 2 0 1 soic 8-pin package z8f0813sh005eg 8 kb 1 kb 16 18 2 0 1 soic 20-pin package z8f0813hh005eg 8 kb 1 kb 16 18 2 0 1 ssop 20-pin package z8f0813ph005eg 8 kb 1 kb 16 18 2 0 1 pdip 20-pin package z8f0813sj005eg 8 kb 1 kb 24 18 2 0 1 soic 28-pin package z8f0813hj005eg 8 kb 1 kb 24 18 2 0 1 ssop 28-pin package z8f0813pj005eg 8 kb 1 kb 24 18 2 0 1 pdip 28-pin package table 135. z8 encore! xp f0823 series ordering matrix (continued) part number flash ram i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels uart with irda description
ps024315-1011 p r e l i m i n a r y ordering information z8 encore! xp ? f0823 series product specification 213 z8 encore! xp f0823 series with 4 kb fl ash, 10-bit analog-to-digital converter standard temperature: 0c to 70c z8f0423pb005sg 4 kb 1 kb 6 12 2 4 1 pdip 8-pin package z8f0423qb005sg 4 kb 1 kb 6 12 2 4 1 qfn 8-pin package z8f0423sb005sg 4 kb 1 kb 6 12 2 4 1 soic 8-pin package z8f0423sh005sg 4 kb 1 kb 16 18 2 7 1 soic 20-pin package z8f0423hh005sg 4 kb 1 kb 16 18 2 7 1 ssop 20-pin package z8f0423ph005sg 4 kb 1 kb 16 18 2 7 1 pdip 20-pin package z8f0423sj005sg 4 kb 1 kb 22 18 2 8 1 soic 28-pin package z8f0423hj005sg 4 kb 1 kb 22 18 2 8 1 ssop 28-pin package z8f0423pj005sg 4 kb 1 kb 22 18 2 8 1 pdip 28-pin package extended temperature: ?40c to 105c z8f0423pb005eg 4 kb 1 kb 6 12 2 4 1 pdip 8-pin package z8f0423qb005eg 4 kb 1 kb 6 12 2 4 1 qfn 8-pin package z8f0423sb005eg 4 kb 1 kb 6 12 2 4 1 soic 8-pin package z8f0423sh005eg 4 kb 1 kb 16 18 2 7 1 soic 20-pin package z8f0423hh005eg 4 kb 1 kb 16 18 2 7 1 ssop 20-pin package z8f0423ph005eg 4 kb 1 kb 16 18 2 7 1 pdip 20-pin package z8f0423sj005eg 4 kb 1 kb 22 18 2 8 1 soic 28-pin package z8f0423hj005eg 4 kb 1 kb 22 18 2 8 1 ssop 28-pin package z8f0423pj005eg 4 kb 1 kb 22 18 2 8 1 pdip 28-pin package table 135. z8 encore! xp f0823 series ordering matrix (continued) part number flash ram i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels uart with irda description
ps024315-1011 p r e l i m i n a r y ordering information z8 encore! xp ? f0823 series product specification 214 z8 encore! xp f0823 series with 4 kb flash standard temperature: 0c to 70c z8f0413pb005sg 4 kb 1 kb 6 12 2 0 1 pdip 8-pin package z8f0413qb005sg 4 kb 1 kb 6 12 2 0 1 qfn 8-pin package z8f0413sb005sg 4 kb 1 kb 6 12 2 0 1 soic 8-pin package z8f0413sh005sg 4 kb 1 kb 16 18 2 0 1 soic 20-pin package z8f0413hh005sg 4 kb 1 kb 16 18 2 0 1 ssop 20-pin package z8f0413ph005sg 4 kb 1 kb 16 18 2 0 1 pdip 20-pin package z8f0413sj005sg 4 kb 1 kb 24 18 2 0 1 soic 28-pin package z8f0413hj005sg 4 kb 1 kb 24 18 2 0 1 ssop 28-pin package z8f0413pj005sg 4 kb 1 kb 24 18 2 0 1 pdip 28-pin package extended temperature: ?40c to 105c z8f0413pb005eg 4 kb 1 kb 6 12 2 0 1 pdip 8-pin package z8f0413qb005eg 4 kb 1 kb 6 12 2 0 1 qfn 8-pin package z8f0413sb005eg 4 kb 1 kb 6 12 2 0 1 soic 8-pin package z8f0413sh005eg 4 kb 1 kb 16 18 2 0 1 soic 20-pin package z8f0413hh005eg 4 kb 1 kb 16 18 2 0 1 ssop 20-pin package z8f0413ph005eg 4 kb 1 kb 16 18 2 0 1 pdip 20-pin package z8f0413sj005eg 4 kb 1 kb 24 18 2 0 1 soic 28-pin package z8f0413hj005eg 4 kb 1 kb 24 18 2 0 1 ssop 28-pin package z8f0413pj005eg 4 kb 1 kb 24 18 2 0 1 pdip 28-pin package table 135. z8 encore! xp f0823 series ordering matrix (continued) part number flash ram i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels uart with irda description
ps024315-1011 p r e l i m i n a r y ordering information z8 encore! xp ? f0823 series product specification 215 z8 encore! xp f0823 series with 2 kb fl ash, 10-bit analog-to-digital converter standard temperature: 0c to 70c z8f0223pb005sg 2 kb 512 b 6 12 2 4 1 pdip 8-pin package z8f0223qb005sg 2 kb 512 b 6 12 2 4 1 qfn 8-pin package z8f0223sb005sg 2 kb 512 b 6 12 2 4 1 soic 8-pin package z8f0223sh005sg 2 kb 512 b 16 18 2 7 1 soic 20-pin package z8f0223hh005sg 2 kb 512 b 16 18 2 7 1 ssop 20-pin package z8f0223ph005sg 2 kb 512 b 16 18 2 7 1 pdip 20-pin package z8f0223sj005sg 2 kb 512 b 22 18 2 8 1 soic 28-pin package z8f0223hj005sg 2 kb 512 b 22 18 2 8 1 ssop 28-pin package z8f0223pj005sg 2 kb 512 b 22 18 2 8 1 pdip 28-pin package extended temperature: ?40c to 105c z8f0223pb005eg 2 kb 512 b 6 12 2 4 1 pdip 8-pin package z8f0223qb005eg 2 kb 512 b 6 12 2 4 1 qfn 8-pin package z8f0223sb005eg 2 kb 512 b 6 12 2 4 1 soic 8-pin package z8f0223sh005eg 2 kb 512 b 16 18 2 7 1 soic 20-pin package z8f0223hh005eg 2 kb 512 b 16 18 2 7 1 ssop 20-pin package z8f0223ph005eg 2 kb 512 b 16 18 2 7 1 pdip 20-pin package z8f0223sj005eg 2 kb 512 b 22 18 2 8 1 soic 28-pin package z8f0223hj005eg 2 kb 512 b 22 18 2 8 1 ssop 28-pin package z8f0223pj005eg 2 kb 512 b 22 18 2 8 1 pdip 28-pin package table 135. z8 encore! xp f0823 series ordering matrix (continued) part number flash ram i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels uart with irda description
ps024315-1011 p r e l i m i n a r y ordering information z8 encore! xp ? f0823 series product specification 216 z8 encore! xp f0823 series with 2 kb flash standard temperature: 0c to 70c z8f0213pb005sg 2 kb 512 b 6 12 2 0 1 pdip 8-pin package z8f0213qb005sg 2 kb 512 b 6 12 2 0 1 qfn 8-pin package z8f0213sb005sg 2 kb 512 b 6 12 2 0 1 soic 8-pin package z8f0213sh005sg 2 kb 512 b 16 18 2 0 1 soic 20-pin package z8f0213hh005sg 2 kb 512 b 16 18 2 0 1 ssop 20-pin package z8f0213ph005sg 2 kb 512 b 16 18 2 0 1 pdip 20-pin package z8f0213sj005sg 2 kb 512 b 24 18 2 0 1 soic 28-pin package z8f0213hj005sg 2 kb 512 b 24 18 2 0 1 ssop 28-pin package z8f0213pj005sg 2 kb 512 b 24 18 2 0 1 pdip 28-pin package extended temperature: ?40c to 105c z8f0213pb005eg 2 kb 512 b 6 12 2 0 1 pdip 8-pin package z8f0213qb005eg 2 kb 512 b 6 12 2 0 1 qfn 8-pin package z8f0213sb005eg 2 kb 512 b 6 12 2 0 1 soic 8-pin package z8f0213sh005eg 2 kb 512 b 16 18 2 0 1 soic 20-pin package z8f0213hh005eg 2 kb 512 b 16 18 2 0 1 ssop 20-pin package z8f0213ph005eg 2 kb 512 b 16 18 2 0 1 pdip 20-pin package z8f0213sj005eg 2 kb 512 b 24 18 2 0 1 soic 28-pin package z8f0213hj005eg 2 kb 512 b 24 18 2 0 1 ssop 28-pin package z8f0213pj005eg 2 kb 512 b 24 18 2 0 1 pdip 28-pin package table 135. z8 encore! xp f0823 series ordering matrix (continued) part number flash ram i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels uart with irda description
ps024315-1011 p r e l i m i n a r y ordering information z8 encore! xp ? f0823 series product specification 217 z8 encore! xp f0823 series with 1 kb fl ash, 10-bit analog-to-digital converter standard temperature: 0c to 70c z8f0123pb005sg 1 kb 256 b 6 12 2 4 1 pdip 8-pin package z8f0123qb005sg 1 kb 256 b 6 12 2 4 1 qfn 8-pin package z8f0123sb005sg 1 kb 256 b 6 12 2 4 1 soic 8-pin package z8f0123sh005sg 1 kb 256 b 16 18 2 7 1 soic 20-pin package z8f0123hh005sg 1 kb 256 b 16 18 2 7 1 ssop 20-pin package z8f0123ph005sg 1 kb 256 b 16 18 2 7 1 pdip 20-pin package z8f0123sj005sg 1 kb 256 b 22 18 2 8 1 soic 28-pin package z8f0123hj005sg 1 kb 256 b 22 18 2 8 1 ssop 28-pin package z8f0123pj005sg 1 kb 256 b 22 18 2 8 1 pdip 28-pin package extended temperature: ?40c to 105c z8f0123pb005eg 1 kb 256 b 6 12 2 4 1 pdip 8-pin package z8f0123qb005eg 1 kb 256 b 6 12 2 4 1 qfn 8-pin package z8f0123sb005eg 1 kb 256 b 6 12 2 4 1 soic 8-pin package z8f0123sh005eg 1 kb 256 b 16 18 2 7 1 soic 20-pin package z8f0123hh005eg 1 kb 256 b 16 18 2 7 1 ssop 20-pin package z8f0123ph005eg 1 kb 256 b 16 18 2 7 1 pdip 20-pin package z8f0123sj005eg 1 kb 256 b 22 18 2 8 1 soic 28-pin package z8f0123hj005eg 1 kb 256 b 22 18 2 8 1 ssop 28-pin package z8f0123pj005eg 1 kb 256 b 22 18 2 8 1 pdip 28-pin package table 135. z8 encore! xp f0823 series ordering matrix (continued) part number flash ram i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels uart with irda description
ps024315-1011 p r e l i m i n a r y ordering information z8 encore! xp ? f0823 series product specification 218 z8 encore! xp f0823 series with 1 kb flash standard temperature: 0c to 70c z8f0113pb005sg 1 kb 256 b 6 12 2 0 1 pdip 8-pin package z8f0113qb005sg 1 kb 256 b 6 12 2 0 1 qfn 8-pin package z8f0113sb005sg 1 kb 256 b 6 12 2 0 1 soic 8-pin package z8f0113sh005sg 1 kb 256 b 16 18 2 0 1 soic 20-pin package z8f0113hh005sg 1 kb 256 b 16 18 2 0 1 ssop 20-pin package z8f0113ph005sg 1 kb 256 b 16 18 2 0 1 pdip 20-pin package z8f0113sj005sg 1 kb 256 b 24 18 2 0 1 soic 28-pin package z8f0113hj005sg 1 kb 256 b 24 18 2 0 1 ssop 28-pin package z8f0113pj005sg 1 kb 256 b 24 18 2 0 1 pdip 28-pin package extended temperature: ?40c to 105c z8f0113pb005eg 1 kb 256 b 6 12 2 0 1 pdip 8-pin package z8f0113qb005eg 1 kb 256 b 6 12 2 0 1 qfn 8-pin package z8f0113sb005eg 1 kb 256 b 6 12 2 0 1 soic 8-pin package z8f0113sh005eg 1 kb 256 b 16 18 2 0 1 soic 20-pin package z8f0113hh005eg 1 kb 256 b 16 18 2 0 1 ssop 20-pin package z8f0113ph005eg 1 kb 256 b 16 18 2 0 1 pdip 20-pin package z8f0113sj005eg 1 kb 256 b 24 18 2 0 1 soic 28-pin package z8f0113hj005eg 1 kb 256 b 24 18 2 0 1 ssop 28-pin package z8f0113pj005eg 1 kb 256 b 24 18 2 0 1 pdip 28-pin package table 135. z8 encore! xp f0823 series ordering matrix (continued) part number flash ram i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels uart with irda description
ps024315-1011 p r e l i m i n a r y ordering information z8 encore! xp ? f0823 series product specification 219 z8 encore! xp f0823 series development kit z8f08a28100kitg z8 encore! xp f082a series development kit (20- and 28-pin) z8f04a28100kitg z8 encore! xp f042a series development kit (20- and 28-pin) z8f04a08100kitg z8 encore! xp f042a series development kit (8-pin) zusbsc00100zacg usb smart cable accessory kit zusboptsc01zacg opto-isolated u sb smart cable accessory kit zenetsc0100zacg ethernet smart cable accessory kit table 135. z8 encore! xp f0823 series ordering matrix (continued) part number flash ram i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels uart with irda description
ps024315-1011 p r e l i m i n a r y ordering information z8 encore! xp ? f0823 series product specification 220 part number su ffix designations zilog part numbers consist of a number of components, as indicated in the following example. example. part number z8f0423sh005sg is an 8-bit 20 mhz flash mcu with 4 kb of program memory and equipped with 6?22 i/ o lines and 4?8 adc channels in a 20-pin soic package, opera ting within a 0oc to +70oc temper ature range and built using lead- free solder. z8 f 04 23 s h 005 s g environmental flow ? g = green plastic packaging compound temperature range s = standard, 0c to 70c ? e = extended, ?40c to +105c speed ? 020 = 20 mhz pin count? b = 8 h = 20 ? j = 28 package h = ssop p = pdip ? s = soic device type 23 = 6?22 i/o lines, 4?8 adc channels 13 = 6?24 i/o lines, no adc channels memory size ? 08 = 8 kb flash, 1 kb ram 04 = 4 kb flash, 1 kb ram 02 = 2 kb flash, 512 b ram 01 = 1 kb flash, 256 b ram memory type ? f = flash device family z8 = zilog?s 8-bit microcontroller
ps024315-1011 p r e l i m i n a r y index z8 encore! xp ? f0823 series product specification 221 index numerics 10-bit adc 4 a absolute maximum ratings 196 ac characteristics 200 adc 178 architecture 121 block diagram 122 continuous conversion 124 control register 126, 129 control register definitions 126 data high byte register 130 data low bits register 131 electrical characteristics and timing 203 operation 122 single-shot conversion 123 adcctl register 126, 129 adcdh register 130 adcdl register 131 adcx 178 add 178 add - extended addressing 178 add with carry 178 add with carry - extended addressing 178 additional symbols 177 address space 13 addx 178 analog signals 10 analog-to-digital co nverter (adc) 121 and 181 andx 181 arithmetic instructions 178 assembly language programming 174 assembly language syntax 175 b b 177 b 176 baud rate generator, uart 108 bclr 179 binary number suffix 177 bit 179 bit 176 clear 179 manipulation instructions 179 set 179 set or clear 179 swap 179 test and jump 181 test and jump if non-zero 181 test and jump if zero 181 bit jump and test if non-zero 181 bit swap 181 block diagram 3 block transfer instructions 179 brk 181 bset 179 bswap 179, 181 btj 181 btjnz 181 btjz 181 c call procedure 181 capture mode 89 capture/compare mode 89 cc 176 ccf 180 characteristics, electrical 196 clear 180 clr 180 com 181 compare 89 compare - extended addressing 178 compare mode 89 compare with carry 178
ps024315-1011 p r e l i m i n a r y index z8 encore! xp ? f0823 series product specification 222 compare with carry - ex tended addressing 178 complement 181 complement carry flag 179, 180 condition code 176 continuous conversion (adc) 124 continuous mode 88 control register definition, uart 108 control registers 13, 16 counter modes 89 cp 178 cpc 178 cpcx 178 cpu and peripheral overview 4 cpu control instructions 180 cpx 178 customer support 230 d da 176, 178 data memory 15 dc characteristics 197 debugger, on-chip 156 dec 178 decimal adjust 178 decrement 178 decrement and jump non-zero 181 decrement word 178 decw 178 destination operand 177 device, port availability 33 di 180 direct address 176 disable interrupts 180 djnz 181 dst 177 e ei 180 electrical characteristics 196 adc 203 flash memory and timing 202 gpio input data sample timing 204 watchdog timer 202, 204 enable interrupt 180 er 176 extended addressing register 176 external pin reset 25 ez8 cpu features 4 ez8 cpu instruction classes 178 ez8 cpu instruction notation 176 ez8 cpu instruction set 174 ez8 cpu instruction summary 182 f fctl register 141, 148, 149 features, z8 encore! 1 first opcode map 194 flags 177 flags register 177 flash controller 4 option bit address space 149 option bit configuration - reset 146 program memory address 0000h 149 program memory address 0001h 150 flash memory 134 arrangement 135 byte programming 139 code protection 137 configurations 134 control register definitions 141, 148 controller bypass 140 electrical characteristics and timing 202 flash control register 141, 148, 149 flash option bits 138 flash status register 142 flow chart 136 frequency high and low byte registers 144 mass erase 139 operation 135 operation timing 137 page erase 139 page select register 142, 144 fps register 142, 144 fstat register 142
ps024315-1011 p r e l i m i n a r y index z8 encore! xp ? f0823 series product specification 223 g gated mode 89 general-purpose i/o 33 gpio 4, 33 alternate functions 34 architecture 34 control register definitions 40 input data sample timing 204 interrupts 40 port a-c pull-up enable sub-registers 47, 48, 49 port a-h address registers 41 port a-h alternate fu nction sub-registers 43 port a-h control registers 42 port a-h data direction sub-registers 43 port a-h high drive enable sub-registers 45 port a-h input data registers 50 port a-h output control sub-registers 44 port a-h output data registers 51 port a-h stop mode re covery sub-registers 46 port availability by device 33 port input timing 205 port output timing 206 h h 177 halt 180 halt mode 31, 180 hexadecimal number prefix/suffix 177 i i2c 4 im 176 immediate data 176 immediate operand prefix 177 inc 178 increment 178 increment word 178 incw 178 indexed 177 indirect address prefix 177 indirect register 176 indirect register pair 176 indirect working register 176 indirect working register pair 176 infrared encoder/decoder (irda) 117 instruction set 174 instruction set, ez8 cpu 174 instructions adc 178 adcx 178 add 178 addx 178 and 181 andx 181 arithmetic 178 bclr 179 bit 179 bit manipulation 179 block transfer 179 brk 181 bset 179 bswap 179, 181 btj 181 btjnz 181 btjz 181 call 181 ccf 179, 180 clr 180 com 181 cp 178 cpc 178 cpcx 178 cpu control 180 cpx 178 da 178 dec 178 decw 178 di 180 djnz 181 ei 180 halt 180 inc 178 incw 178 iret 181 jp 181
ps024315-1011 p r e l i m i n a r y index z8 encore! xp ? f0823 series product specification 224 ld 180 ldc 180 ldci 179, 180 lde 180 ldei 179 ldx 180 lea 180 load 180 logical 181 mult 179 nop 180 or 181 orx 181 pop 180 popx 180 program control 181 push 180 pushx 180 rcf 179, 180 ret 181 rl 181 rlc 181 rotate and shift 181 rr 182 rrc 182 sbc 179 scf 179, 180 sra 182 srl 182 srp 180 stop 180 sub 179 subx 179 swap 182 tcm 179 tcmx 179 tm 179 tmx 179 trap 181 watchdog timer refresh 180 xor 181 xorx 181 instructions, ez8 classes of 178 interrupt control register 68 interrupt controller 54 interrupt controller architecture 54 interrupt assertion types 57 interrupt vectors and priority 57 operation 56 register definitions 59 software interrupt assertion 58 interrupt edge select register 66 interrupt request 0 register 59 interrupt request 1 register 60 interrupt request 2 register 61 interrupt return 181 interrupt vector listing 54 interrupts uart 105 ir 176 ir 176 irda architecture 117 block diagram 117 control register definitions 120 operation 117 receiving data 119 transmitting data 118 iret 181 irq0 enable high and low bit registers 61 irq1 enable high and low bit registers 63 irq2 enable high and low bit registers 65 irr 176 irr 176 j jp 181 jump, conditional, relative, and relative conditional 181 l ld 180 ldc 180 ldci 179, 180 lde 180
ps024315-1011 p r e l i m i n a r y index z8 encore! xp ? f0823 series product specification 225 ldei 179, 180 ldx 180 lea 180 load 180 load constant 179 load constant to/fro m program memory 180 load constant with auto-increment addresses 180 load effective address 180 load external data 180 load external data to/fro m data memory and auto- increment addresses 179 load external to/from data memory and auto-incre- ment addresses 180 load instructions 180 load using extended addressing 180 logical and 181 logical and/extended addressing 181 logical exclusive or 181 logical exclusive or/extended addressing 181 logical instructions 181 logical or 181 logical or/extended addressing 181 low power modes 30 m master interrupt enable 56 memory data 15 program 13 mode capture 89 capture/compare 89 continuous 88 counter 89 gated 89 one-shot 88 pwm 89 modes 89 mult 179 multiply 179 multiprocessor mode, uart 103 n nop (no operation) 180 notation b 176 cc 176 da 176 er 176 im 176 ir 176 ir 176 irr 176 irr 176 p 176 r 176 r 176 ra 177 rr 177 rr 177 vector 177 x 177 notational shorthand 176 o ocd architecture 156 auto-baud detector/generator 159 baud rate limits 160 block diagram 156 breakpoints 161 commands 162 control register 166 data format 159 dbg pin to rs-232 interface 157 debug mode 158 debugger break 181 interface 157 serial errors 160 status register 168 timing 207 ocd commands execute instruction (12h) 166 read data memory (0dh) 165 read ocd control re gister (05h) 163
ps024315-1011 p r e l i m i n a r y index z8 encore! xp ? f0823 series product specification 226 read ocd revision (00h) 163 read ocd status register (02h) 163 read program counter (07h) 164 read program memory (0bh) 164 read program memory crc (0eh) 165 read register (09h) 164 read runtime counter (03h) 163 step instruction (10h) 165 stuff instruction (11h) 166 write data memory (0ch) 165 write ocd control register (04h) 163 write program counter (06h) 163 write program memory (0ah) 164 write register (08h) 164 on-chip debugger (ocd) 156 on-chip debugger signals 10 one-shot mode 88 opcode map abbreviations 193 cell description 192 first 194 second after 1fh 195 operational description 21, 30, 33, 69, 91, 97, 117, 121, 132, 134, 146, 156, 169, 173 or 181 ordering information 211 orx 181 p p 176 packaging 210 part selection guide 2 pc 177 peripheral ac and dc electrical characteristics 201 pin characteristics 11 pin descriptions 7 polarity 176 pop 180 pop using extended addressing 180 popx 180 port availability, device 33 port input timing (gpio) 205 port output timing, gpio 206 power supply signals 10 power-on and voltage brownout electrical charac- teristics and timing 201 power-on reset (por) 23 program control instructions 181 program counter 177 program memory 13 push 180 push using extended addressing 180 pushx 180 pwm mode 89 pxaddr register 41 pxctl register 42 r r 176 r 176 ra register address 177 rcf 179, 180 receive irda data 119 receiving uart data-inte rrupt-driven method 102 receiving uart data-polled method 101 register 176 adc control (adcctl) 126, 129 adc data high byte (adcdh) 130 adc data low bits (adcdl) 131 flash control (fctl) 141, 148, 149 flash high and low byte (ffreqh and fre- eql) 144 flash page select (fps) 142, 144 flash status (fstat) 142 gpio port a-h address (pxaddr) 41 gpio port a-h alternate function sub-registers 44 gpio port a-h control address (pxctl) 42 gpio port a-h data direction sub-registers 43 ocd control 166 ocd status 168 uartx baud rate high byte (uxbrh) 115 uartx baud rate lo w byte (uxbrl) 115 uartx control 0 (uxctl0) 112, 115
ps024315-1011 p r e l i m i n a r y index z8 encore! xp ? f0823 series product specification 227 uartx control 1 (uxctl1) 113 uartx receive data (uxrxd) 109 uartx status 0 (uxstat0) 110 uartx status 1 (uxstat1) 111 uartx transmit data (uxtxd) 109 watchdog timer control (wdtctl) 94, 133 watch-dog timer control (wdtctl) 172 watchdog timer reload high byte (wdth) 95 watchdog timer reload low byte (wdtl) 95 watchdog timer reload upper byte (wdtu) 95 register file 13 register pair 177 register pointer 177 reset and stop mode characteristics 21 and stop mode recovery 21 carry flag 179 sources 23 ret 181 return 181 rl 181 rlc 181 rotate and shift instructions 181 rotate left 181 rotate left through carry 181 rotate right 182 rotate right th rough carry 182 rp 177 rr 177, 182 rr 177 rrc 182 s sbc 179 scf 179, 180 second opcode map after 1fh 195 set carry flag 179, 180 set register pointer 180 shift right arithmetic 182 shift right logical 182 signal descriptions 9 single-sho conversion (adc) 123 software trap 181 source operand 177 sp 177 sra 182 src 177 srl 182 srp 180 stack pointer 177 stop 180 stop mode 30, 180 stop mode recovery sources 26 using a gpio port pin transition 27, 28 using watchdog timer time-out 27 sub 179 subtract 179 subtract - extended addressing 179 subtract with carry 179 subtract with carry - extended addressing 179 subx 179 swap 182 swap nibbles 182 symbols, additional 177 t tcm 179 tcmx 179 test complement under mask 179 test complement under mask - extended addressing 179 test under mask 179 test under mask - extended addressing 179 timer signals 9 timers 69 architecture 70 block diagram 70 capture mode 78, 79, 89 capture/compare mode 82, 89 compare mode 80, 89 continuous mode 71, 88 counter mode 72, 73 counter modes 89 gated mode 81, 89
ps024315-1011 p r e l i m i n a r y index z8 encore! xp ? f0823 series product specification 228 one-shot mode 70, 88 operating mode 70 pwm mode 75, 76, 89 reading the timer count values 83 reload high and low byte registers 84 timer control register definitions 83 timer output signal operation 83 timers 0-3 control registers 86, 87 high and low byte registers 83, 86 tm 179 tmx 179 tools, hardware and software 220 transmit irda data 118 transmitting uart data-polled method 99 transmitting uart dat-interrupt-driven method 100 trap 181 u uart 4 architecture 97 baud rate generator 108 control register definitions 108 controller signals 9 interrupts 105 multiprocessor mode 103 receiving data using in terrupt-driven method 102 receiving data using the polled method 101 transmitting data using the interrupt-driven method 100 transmitting data using the polled method 99 x baud rate high and low registers 115 x control 0 and control 1 registers 112 x status 0 and status 1 registers 110, 111 uxbrh register 115 uxbrl register 115 uxctl0 register 112, 115 uxctl1 register 113 uxrxd register 109 uxstat0 register 110 uxstat1 register 111 uxtxd register 109 v vector 177 voltage brownout reset (vbr) 24 w watchdog timer approximate time-out delay 91 cntl 24 control register 94, 171 electrical characteristics and timing 202, 204 interrupt in normal operation 92 interrupt in stop mode 92 refresh 92, 180 reload unlock sequence 93 reload upper, high and low registers 94 reset 25 reset in normal operation 93 reset in stop mode 93 time-out response 92 watchdog timer control register (wdtctl) 94 wdtctl register 94, 133, 172 wdth register 95 wdtl register 95 wdtu register 95 working register 176 working register pair 177 x x 177 xor 181 xorx 181 z z8 encore! block diagram 3 features 1
ps024315-1011 p r e l i m i n a r y index z8 encore! xp ? f0823 series product specification 229 part selection guide 2
ps024315-1011 p r e l i m i n a r y customer support z8 encore! xp ? f0823 series product specification 230 customer support to share comments, get your technical questio ns answered, or report issues you may be experiencing with our products, please visit zilog?s technical support page at ? http://support.zilog.com . to learn more about this produc t, find additional documentati on, or to discover other fac- ets about zilog product offerings, pl ease visit the zilog knowledge base at http:// zilog.com/kb or consider participating in the zilog forum at http://zilog.com/forum . this publication is subject to replacement by a later edition. to determine whether a later edition exists, please vis it the zilog website at http://www.zilog.com .

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